JPH0352677B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address selection circuit, and more particularly to an address selection circuit suitable for high-speed selection of a memory array.

[Conventional technology]

Conventionally, as a circuit for selecting the address of a MOS circuit,
A circuit is known that is driven by an ECL circuit and converts the signal level of the ECL circuit (hereinafter referred to as ECL level) to the signal level of a MOS circuit (hereinafter referred to as MOS level).

FIG. 8 shows such an address selection circuit. In FIG. 8, the address conversion buffer circuit 1 includes a detection circuit DET that converts an ECL level input signal to a MOS level, detects the ECL level input signal, an amplifier circuit AMP that amplifies the output of the detection circuit DET to the MOS level, and next stage circuit (predecoder 2)
It consists of a buffer circuit BUF that drives.
Each address buffer circuit 1 receives a 1-bit input signal.
A ₁ to A _o are input, and the two output lines are "1" and "0" respectively when the input is "0", and when the input is "1"
When this happens, the opposite “0” and “1” are output. Predecoder 2 has 4 2 inputs (2 are omitted in the figure)
It consists of a NAND gate and an inverter that drives the next stage circuit (decoder 3). The outputs of the two address buffer circuits 1 are given to the predecoder 2, and depending on the combination of values taken by the 2-bit input signals (for example, A ₁ and A ₂ ), only one of the four output lines is set to " Outputs a 1” (high level) signal. The role of the predecoder 2 is to reduce the number of inputs of the decoder 3, which is composed of a multi-input NAND gate, that is, the number of transistors connected in series, and to obtain high-speed operation of the decoder 3. Normally, the number of input signals to be precoded is reduced. It is said that 2 bits is optimal. The inverting buffer 4 is composed of an odd number of stages (usually three stages) of inverters in order to invert the output of the decoder 3 and drive a large load of the next stage circuit, the memory array 5. As a result, the addresses indicated by the input signals A ₁ to A _o of the memory array 5 are selected.

[Problems to be solved by the invention] The conventional configuration shown in _FIG .
A _o ), the output of inverting buffer 4 2 ⁿ
When performing an address selection operation with only one of the books at a high level, the number of circuit stages increases (9 in Figure 8).
2), there is a drawback that the delay time for address selection operation increases significantly. Furthermore, since all the circuits after the amplifier circuit AMP of the address buffer circuit 1 operate with MOS level signals (large amplitude operation), the time required for rise and fall increases, making it difficult to speed up the address selection operation. be.

The present invention aims to solve the problem of the conventional method and speed up the address selection operation.

[Means for solving problems]

The present invention includes: a first decoding means for detecting and predecoding an input signal; a level shifting means for level-shifting the output of the first decoding means;
a second for decoding and amplifying the output of the level shifting means;
The second decoding means has four stages: a decoding means, and an inverting buffer means for inverting the output of the second decoding means.

[Effect]

By reducing the number of circuit stages to the above-mentioned four stages and performing small amplitude operation up to the input of the third stage decoding means, the address selection operation can be made faster.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the invention. In FIG. 1, 5 is a memory array, 6, 6' are predecoders, 7, 7' are level shift circuits, 8 is a decoder,
9 is an inverting buffer, and A ₁ to A _o are input signals.

As shown in FIG. 2, the predecoder 6 is composed of a current switching type logic circuit with a collector dotting configuration, and in _{FIG .}
The case of bit is shown. In FIG. 2, two bipolar transistors whose collectors are common to the load Z are connected to each output V ₀₆ (m) (m=1 to 4) of the predecoder 6, and each output is selected. Depending on the bit pattern of the input signal, either the input signal A ₁ or A ₂ or the ECL level reference voltage V _R (approximately -1.3V) is applied to the base of each transistor, and the emitter is connected to the current source circuit I. Connected to either I ₆ (1) or I ₆ (2).

Now, the bit patterns of input signals A ₁ and A ₂ are (0,
0) (“0” means the input signal level is approximately -1.6V,
"1" means input signal level is approximately -0.8V), output V ₀₆ 1
is selected, and similarly, when the bit patterns of input signals A ₁ and A ₂ are (01), (10), and (11), the output V ₀₆
(2), V ₀₆ (3), and V ₀₆ (4) are selected. At this time,
Bipolar transistor connected to output V ₀₆ 1
The input signals A ₁ and Q ₆ (2) are connected to the bases of Q 6 (1) and Q ₆ (2), respectively.
A ₂ is applied, and the emitters are each connected to a current source circuit I ₆
(1), connected to I ₂ (2). Below, input signal A and reference voltage _VR are applied to the bases of bipolar transistors Q _{6 (} 3) and Q ₆ (4), which are connected to output V 06 (2), respectively, and are connected to V ₀₆ (3). V _R and A ₂ are applied to the bases of Q ₆ (5) and Q ₆ (6), respectively, and both are applied to the bases of Q ₆ (7) and Q ₆ (8) connected to V ₀₆ (4). V _R is applied.
Also, bipolar transistors Q ₆ (1), Q ₆ (3), Q ₆ (5),
The emitter of Q ₆ (7) is made common and the current source circuit I ₆ (1)
The emitters of Q ₆ (2), Q ₆ (4), Q ₆ (6), and Q ₆ (8) are commoned and connected to the current source circuit I ₆ (2). That is, the bases of the two bipolar transistors connected to each output V ₀₆ (m) (m = 1 to 4) correspond to the bit patterns of the input signals A ₁ and A ₂ when each output is selected. So, when that bit is “0”, the input signal is (when the first bit is “0”, _A1 is
When the second bit is “0”, _A2 ) is applied,
When that bit is "1", reference voltage V _R is applied. On the other hand, regarding the emitters, all emitters of the transistors corresponding to the first bit are connected to the first current source circuit I ₆ (1), and all emitters of the transistors corresponding to the second bit are connected to the second current source circuit I 6 (1). Connected to circuit I ₆ (2). Then for each output
Regarding the selection operation of V ₀₆ (m) (m=1 to 4),
When the bit patterns of input signals A ₁ and A ₂ are (00), both bipolar transistors Q ₆ (1) and Q ₆ (2) are necessarily non-conductive, so the voltage of output V ₀₆ (1) becomes V _CC =0V. Become,
For the other outputs V ₀₆ (2), V ₀₆ (3), and V ₀₆ (4), one or both of the bipolar transistors connected to the outputs are conductive, so current flows to load Z, and the voltage of load Z Due to the drop, the output voltage is approximately -
0.8V and output V ₀₆ (1) is selected. other output
The selection operations for V ₀₆ (2), V ₀₆ (3), and V ₀₆ (4) are performed in the same manner. The role of the diode in load Z is to clamp the output voltage to approximately -0.8V when not selected.

Above, in Fig. 2, the configuration and operation of the predecoder have been explained for the case where the input signal is 2 bits (A ₁ , A ₂ ), but the same applies when the input signal is 3 bits or more. If the output
V ₀₆ is 2 ⁱ , each output V ₀₆ (m) (m = 1 ~ 2 ⁱ )
The number of bipolar transistors connected to is i, and the number of current source circuits is also i.

Note that for the predecoder 6', the remaining input signals other than the input signals A ₁ to _{A i} of the predecoder 6
The circuit configuration is similar to that of the precoder 6 only that A _i+1 to A _o are applied. Predecoder 6 output V ₀₆
(m) (m= ^1-2i ) is level-shifted to the lower potential side by the level shift circuit 7, and the output V ₀₇ (m) (m= ^1-2i ) of the level shift circuit 7 has an amplitude of about 0.8V. is applied to the decoder 8 as a small amplitude signal.

As shown in FIG. 3, the level shift circuit 7 is composed of an emitter follower, a plurality of diodes, and a load resistor R connected in series. The amount of level shift by the level shift circuit 7 is controlled by the number of diodes and the value of the load resistance. Note that the level shift circuit 7'
has the same circuit configuration as level shift circuit 7, but the number of series-connected diodes is increased to increase the amount of level shift.

As shown in FIG. 4, the decoder 8 is composed of a current switching type logic circuit with a series gate configuration.
Outputs of level shift circuits 7 and 7' V ₀₇ (1) to _{V 07}
(2 ⁱ ) and V ₀₇ ′(1) to V ₀₇ ′(2 ^n-1 ) are input, and their combination produces 2 ⁿ outputs (V ₀₈ (1) to V ₀₈
A selection operation is performed by setting one of ( _2o )) to a low level. The series gate of the decoder 8 is composed of an upper gate 10, a lower gate 11, and a current source circuit _I8 connected in series. The upper gate 10 is driven by the outputs V ₀₇ (1) to V ₀₇ (2 ⁱ ) of the level shift circuit 7, and the lower gate 11 is driven by the outputs V ₀₇ ′(1) to _{V 07} ′( 2n ^-1 ). for example,
Among the outputs of the level shift circuit 7, only V ₀₇ (1) is
Furthermore, when only V ₀₇ '(1) among the outputs of the level shift circuit 7' is at a high level, the bipolar transistor Q ₁₀ (1) whose base is connected to V ₀₇ (1) and whose base is
Bipolar transistor connected to V ₀₇ ′(1)
Q ₁₁ (1) becomes conductive, and a current path is formed between power supplies V _CC and V _EE via resistor R ₁₀ , bipolar transistors Q ₁₀ (1), Q ₁₁ (1), and current source circuit I ₈ be done. Therefore, only the output ₀₈ (1) of the decoder 8 becomes low level due to the voltage drop across the resistor R ₁₀ , and a selection operation is performed. Now, if the high level of the output V ₀₈ (1) of the level shift circuit 7 is set to -3V or less (if the number of diodes in the level shift circuit 7 is set to three, the high level of the output of the level shift circuit 7 will be approximately - 3.2V),
The low level of the output V ₀₈ (1) of the decoder 8 can be about -3V, the amplitude of the output V ₀₈ (1) is about 3V (the high level of the output V ₀₈ (1) is 0V), and the next The inverting buffer 9, which is a stage circuit, can be sufficiently driven by a MOS circuit. That is, the decoder 8 can perform an amplification operation between input and output simultaneously with a selection operation.

The inverting buffer 9 is the output V ₀₈ (1) of the decoding 8
This circuit inverts V ₀₈ (2 ⁿ ) and drives the memory array 5, which is a large burden in the next stage, with a MOS level signal. Since the decoder 8 in the previous stage is configured using a bipolar transistor with a large load driving force, the inversion buffer 9 is configured using a MOS transistor with a large gate width.
One stage of inverter configured using transistors can drive the next stage memory array 5 at high speed. or,
The inverting buffer can also be configured with an inverter using a composite circuit of MOS transistors and bipolar transistors.

As mentioned above, in the present invention, the address selection circuit receives the ECL level input signal at the first stage predecoders 6 and 6'.
A ₁ to A _o detection operation and pre-decoding operation are performed,
The level shift circuits 7 and 7' in the second stage perform a level shift operation, the decoder 8 in the third stage performs an address selection operation and an amplification operation, and the inverting buffer 9 in the fourth stage performs a level shift operation.
By adopting the configuration in which the memory array 5 is driven by the number of circuit stages, the number of circuit stages is reduced, and furthermore, since the input to the third stage decoder 8 is operated with a small amplitude, the address selection operation can be made faster.

FIGS. 5 and 6 show examples of configurations in which the current source circuits of the predecoders 6 and 6' and the decoder 8 are provided with a function to cut off the current during standby, respectively. Figure 5 shows an example of a current source circuit configured with a MOS transistor T ₆ (1), whose drain is connected to the _common emitter circuit, its source is connected to the power supply V _EE , and its gate is connected to a control signal. V _CS is applied.
During operation, the control signal V _CS is at a high level, and the MOS transistor T ₆ (1) is conductive, operating as a current source for the common emitter circuit. On the other hand, during standby, the control signal V _CS is at a low level, and the MOS transistor _T6
(1) becomes non-conductive, cutting off the current from the common emitter circuit.

Figure 6 shows the current source circuit using a bipolar transistor.
This is an example in which a bipolar transistor Q ₆ (9) and a MOS transistor _{T 6} (2) are connected in series.
The collector of is connected to the common emitter circuit, the constant voltage V _BB is applied to the base, the source of the MOS transistor T ₆ (2) is connected to the power supply V _EE , and the control signal V _CS is applied to the gate. The control of the current source circuit during operation and standby by the control signal V _CS is similar to the configuration example shown in FIG.

FIG. 7 shows a configuration example in which a function to cut off the current during standby is added to the level shift circuits 7 and 7', and the load resistance R of the level shift circuit shown in FIG. 3 is replaced by a MOS transistor T ₇ (1 ).
A control signal is applied to the gate of MOS transistor T ₇ (1).
V _CS is applied, and the control of the MOS transistor T ₇ (1) during operation and standby by the control signal V _CS is similar to the configuration example of the current source circuit shown in FIG.

As described above, the predecoders 6 and 6' insert MOS transistors into the current pulses of the current source circuit of the decoder 8 and the loads of the level shift circuits 7 and 7', respectively, and control the control applied to the gates of the MOS transistors. By adding a function to cut off the current during standby using the signal V _CS , it is possible to achieve low power consumption during standby.

Although MOS transistors are used in the embodiments described above, it is also possible to use other types of field effect transistors.

〔Effect of the invention〕

As explained above, the address selection circuit of the present invention is composed of four stages of circuits: a predecoder, a level shift circuit, a decoder, and an inverting buffer, so the number of circuit stages is small, and the operation up to the input of the decoder is small. , the address selection operation can be speeded up.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a diagram showing a specific example of the predecoder in FIG. 1, FIG. 3 is a diagram showing a specific example of the level shift circuit in FIG. 1, and FIG. 4 is a diagram showing a specific example of the decoder in FIG. 1. , Fig. 5 and Fig. 6 are diagrams showing an example in which a standby current cutoff function is added to the current source circuit, and Fig. 7
The figure shows an example in which a standby current cutting function is added to the level shift circuit, and FIG. 8 shows a conventional example. 5...Memory array, 6...Predecoder, 7
... Level shift circuit, 8 ... Decoder, 9 ...
Reverse battle.

Claims (1)

[Claims] 1. A first decoding means for detecting and predecoding an input signal using a current switching type logic circuit having a collector dotting configuration; and a level shifting means for level-shifting an output signal from the first decoding means to a lower potential side. , second decoding means for decoding and amplifying the output signal from the level shifting means using a current switching type logic circuit having a series gate configuration; and inverting buffer means for inverting the output signal from the second decoding means. An address selection circuit comprising: