JPH0352678B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a RAM read/write circuit that is faster and more compact.

(Summary of the Invention) The present invention relates to a RAM read/write circuit for reading and writing data to the bit line of a memory cell. The operation delay caused by the on-resistance of the switch connected to the circuit has been eliminated by installing the switch on the input side of the inverter that makes up the sense amplifier and in the feedback loop. By sharing the write circuit, the structure is simplified and the size is reduced.

(Prior Art) FIG. 3a shows the configuration of a conventional RAM read/write circuit, and 11 and 12 are bit lines connected to memory cells. Note that mutually complementary data signals are input and output to the bit lines 11 and 12. I ₁ and I ₂ are inverters that constitute a flip-flop type sense amplifier,
The input terminals and output terminals of the inverters I 1 and I 2 are connected to each other, and the output terminals of the inverters I ₁ and I ₂ are connected to the data output terminals 17 and 1
8, respectively, and to bit lines 11 and 12 via switches S ₁ and S ₂ , respectively. Note that mutually complementary data appears at the data output terminals 17 and 18. On the other hand, I ₃ and I ₄ are inverters constituting a write circuit, whose input terminals are connected to data input terminals 13 and 14 for writing, and whose output terminals are connected to bit lines 11 and 12 via switches S ₃ and S ₄ . It is connected to the. Note that signals complementary to each other are applied to the data input terminals 13 and 14. In addition, 16 is the switch S ₁ , S ₂
and 15 are control signal terminals for switches S ₃ and S _4. When reading, switches S ₁ and S ₂ are on and switches S ₃ and S ₄ are off, and when writing, switches S ₁ and S ₂ are off. A control signal is given so that switches S ₃ and S ₄ are turned on when they are off.

FIG. 3b shows FIG. 3a more specifically, in which M ₁ and M ₃ are transistors forming the inverter I ₁ , and M ₂ and M ₄ are transistors forming the inverter I ₂ . Also, transistors M ₁ , M ₂
One end of is connected to power supply terminal 1, and the transistor
One ends of M ₃ and M ₄ are connected to the ground line via transistor M ₅ , and a signal applied to the control signal terminal 19 controls the on/off of transistor M ₅ to control the operation of the sense amplifier. It's getting old. Regarding other parts, the same parts as in FIG. 3a are given the same reference numerals.

The operation will be explained below. Note that just before operation, it is common to precharge so that the potential difference between the bit lines 11 and 12 and between the sense amplifier output terminals are both 0V.

Therefore, in the read operation, the control terminal 19 is set to a low level, transistor _M5 is turned off, and no power supply current flows to the sense amplifier made up of transistors _M1 to _M4 , and the switch is turned off.
When S ₁ and S ₂ are turned on, the memory cell switches to bit line 11,
12 is transmitted to the sense amplifier. Then, connect bit line 1 between the output terminals of the sense amplifier.
When the output signals from 1 and 12 are generated, the control signal terminal 19 is set to high level to turn on the transistor _M5 . Then, since the flip-flop type sense amplifier is a positive feedback amplifier, this potential difference is amplified, and finally, depending on the read data, one of the data output terminals 17 and 18 is set to the ground level and the other to the power supply potential. .

Also, when writing, switch S ₃ , S ₄
is turned on, and the write data given from the data input terminals 13 and 14 is sent to the inverters I ₃ and I ₄
is applied to bit lines 11 and 12 for writing.

(Problems to be Solved by the Invention) Although the conventional circuit shown in FIG. 3 operates as described above, it has the following drawbacks. That is, FIG. 4 shows an equivalent circuit during each operation of the circuit in FIG. 3a, and a
indicates the read operation, and b indicates the write operation. During the read, as shown in a, the on-resistance of the switches S ₁ and S ₂ is the same as that of the bit lines 11 and 12 and the inverter I ₁ , In addition, during writing, the on-resistance of switches S _{3 and} S ₄ is between the bit lines 11 and 12 and the output terminal of inverters I ₃ and I ₄ as shown in b. It will be inserted between the terminal and the terminal. In general, MOS transistors have a large on-resistance, so in this type of circuit that uses them as a switch, the time constant with the output capacitance of the sense amplifier becomes large, which slows down the determination of the potential at the sense amplifier output point, which slows down the readout speed. This was the cause of deterioration. Furthermore, during writing, the time constant between the on-resistance of switches S ₃ and S ₄ and the bit line parasitic capacitance similarly poses an obstacle to increasing the writing speed.

(Means for Solving the Problems) The present invention was proposed to eliminate the above-mentioned drawbacks, and it replaces the switch that was on the output side of the sense amplifier with the input side that has small parasitic capacitance and is not affected by on-resistance. and a sense amplifier feedback loop to eliminate deterioration in operating speed due to the on-resistance of the switch, speed up reading and writing, and also drive the drive element of the data input terminal by using the sense amplifier as a write circuit during writing. It is an object of the present invention to provide a read/write circuit for RAM that can reduce the capacity and also be miniaturized by omitting a write circuit.

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 1a is a basic configuration diagram showing an embodiment of the present invention, and FIG. 1b is a circuit diagram specifically constructed using MOS transistors. In FIG. 1, 1 is a power supply terminal, 11 and 12 are bit lines, 13 and 14 are data input terminals for writing, and 17 and 18 are data output terminals. , data output terminals 17, 18
Complementary signals are applied to or generated from each of the signals.

In FIG. 1a, the output terminal of inverter I ₁ is connected to one bit line 11 and one data output terminal 17, and is also connected to the input terminal of inverter I ₂ via switch _{S 2} . The output terminal is connected to the other bit line 12 and the other data output terminal 18, and is connected to the inverter _I1.
is connected to the input terminal of the switch _S1 . Also, one data input terminal 13 is a switch.
connected to the input terminal of the inverter I ₁ through S ₃ ,
The other data input terminal 14 is connected via a switch _S4 to the input terminal of an inverter _I2 . Note that 15 and 16 are control signal terminals that control the on/off of switches S ₁ to _{S 4} , which turns on switches S ₁ and S ₂ during reading, turns off switches S ₃ and S 4, and turns off switches S 3 and S ₄ during writing. A control signal is given to turn off the switches S ₁ and S ₂ and turn on the switches S ₃ and S ₄ .

In FIG. 1b, M ₁ and M ₃ are transistors that constitute an inverter I ₁ , and M ₂ and M ₄ are transistors that constitute an inverter I _{2 .}
This is a transistor that makes up the Further, one ends of the transistors M ₁ and M ₂ are connected to the power supply terminal 1, and one ends of the transistors M ₃ and M ₄ are connected to the earth line via the transistor M ₅ . Transistor _M5
It is now possible to control the on/off of the sense amplifier and the operation of the sense amplifier.

In operation, during reading, if the switches S ₁ and S 2 are turned on and the switches S ₃ and S ₄ are turned off by controlling the control signal terminals 15 and ₁₆ , the inputs of the inverters I ₁ and I ₂ are connected to each other. The terminal and the output terminal are connected to form a flip-flop type sense amplifier, and the levels of the bit lines 11 and 12 can be read and output to the output terminals 17 and 18. Furthermore, if the switches S ₁ and S ₂ are turned off and the switches S ₃ and S ₄ are turned on by controlling the control signal terminals 15 and 16 during writing, the inverter
I ₁ and I ₂ can each operate independently, and data is written by inverting the signals applied to data input terminals 13 and 14 and applying them to bit lines 11 and 12.

FIG. 2 shows an equivalent circuit during each of the above operations. During reading, the bit lines 11 and 12 shown in a are directly connected to the output terminals of the inverters I ₁ and I ₂ , and the switch S ₁ and _S2 are provided on the input side, which has small parasitic capacitance and is not affected by on-resistance, so there is no speed deterioration due to the time constant caused by the on-resistance of switches _S1 and _S2 , and the readout speed can be increased. . Furthermore, during writing, as shown in b, the output terminals of inverters I ₁ and I ₂ that operate as write amplifiers are connected to bit lines 11 and 11, respectively.
Since the switches S 3 and S 4 are connected directly to 12, and switches S ₃ and S ₄ are provided on the input side of the sense amplifier, the time constant between the input capacitance and on-resistance of the sense amplifier is small, and therefore the sense amplifier can be set quickly. It is. Furthermore, the driving elements for the data input terminals 13 and 14 are inverters I ₁ and I ₂ that constitute a sense amplifier.
It is sufficient to drive the gate of the transistor in the input stage of the circuit, so it has the advantage that a large amount of driving power is not required. That is, in a sense amplifier circuit, the size of the transistor is usually large for high-speed operation, and the current for inverting the memory cell can be sufficiently supplied by the inverters I ₁ and I ₂ . Therefore, in conventional circuits, the data input terminals 13 and 14 are usually provided with an inverter for the write circuit having a large driving capacity for writing, but in the present invention, the write circuit is not necessary, and there is an advantage that miniaturization can be achieved by reducing the number of elements.

(Effects of the Invention) As described above, in the present invention, by eliminating the switch that was conventionally inserted between the output of the sense amplifier or write circuit and the bit line, the on-resistance of the switch is reduced. Since speed degradation due to constants is eliminated, reading and writing can be performed at high speed. Further, since a write circuit is not required, there is an effect that the circuit can be made smaller.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, in which a is a basic configuration diagram, b is a specific circuit configuration diagram composed of MOS transistors, and FIGS. 2 a and b are reading and writing times of FIG. 3 shows an example of a conventional circuit, a is a basic configuration diagram, b is a specific circuit configuration diagram composed of MOS transistors, and FIGS. 4a and 4b are equivalent circuit diagrams for each case. FIG. 3 is an equivalent circuit diagram for each case of reading and writing in FIG. 3a; 11, 12... Bit line, 13, 14... Data input terminal, 15, 16, 19... Control signal terminal, 17, 18... Data output terminal, 1... Power supply terminal, I ₁ , I ₂ ... Inverter, S ₁ to S ₄ ... switch, M ₁ to _{M 5} ... transistor.

Claims (1)

[Claims] 1 A RAM that is connected to a pair of bit lines, reads signals from the bit lines and outputs them to a pair of data output terminals, and also provides write signals to the bit lines based on signals given from a pair of data input terminals.
A read/write circuit for use in a device includes first and second inverters and first to fourth switches, and connects the output terminal of the first inverter to one bit line and one data output terminal, and connects the output terminal of the first inverter to one bit line and one data output terminal. Connect the input terminal of the inverter via a second switch, connect the output terminal of the second inverter to the other bit line and the other data output terminal, and connect the first switch to the input terminal of the first inverter. one data input terminal is connected to the input terminal of the first inverter via the third switch, and the other data input terminal is connected to the input terminal of the second inverter via the fourth switch. When reading, the first and second switches are turned on and the third and fourth switches are turned off. When writing, the first and second switches are turned off and the third and fourth switches are turned off. A control signal is given to turn it on.
Read/write circuit for RAM.