JPH0512877A - Semiconductor memory circuit - Google Patents

Abstract

(57) [Summary] [Object] A semiconductor memory circuit according to the present invention shortens the charge / discharge time of data when reading data. [Structure] A semiconductor memory circuit according to the present invention has a basic structure of a flip-flop formed by using two inverter circuits each including a transistor and a load element. A control electrode is connected to the output terminal of the inverter circuit, and an output transistor having a signal line connected to the data line is connected to the data line. And a drive transistor for driving the output transistor based on the signal of the read word line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit which can be operated at high speed and is used in computers and various communication devices.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor memory circuit has a FET 21 in which a gate and a source are short-circuited,
FE with 23 as load and drain connected to this load
Two inverter circuits having T22 and T24 as input transistors are connected to form a flip-flop circuit. FETs 25 and 26 are transfer gates,
Depending on the signal (voltage) given to the word line X, the data lines Y, Y and the output terminals (points) A, B of the above-mentioned inverter circuits
Contact with. The voltage V _DD is applied to the drains of the FETs 21 and 23, and the voltage V _DD is applied to the sources of the FETs 22 and 24.
_SS is given. In such a semiconductor memory circuit, in order to read data, a high-level voltage is applied to the word line X to bring the FETs 25 and 26, which are transistor gates into a conductive state, and the potential at the point A to the data line Y The potential of the point is transmitted to the data line Y. Also,
In order to write data, a high level voltage is again applied to the word line X to open the transfer gate, and a signal according to the state to be written is applied to the data lines Y and Y.

[0003]

[SUMMARY OF THE INVENTION Incidentally, in the conventional memory, the data line Y, at least several tens of memory cells are connected to the Y, the data line Y, the length of Y is a few mm
Can extend to Therefore, when reading the memory, for the data lines Y, Y having such a large wiring capacity,
It is necessary to charge and discharge with a small memory cell charge, and in order to perform high speed memory access, this data line Y, Y
The challenge is to reduce charging and charging time.

Therefore, a method of limiting the signal amplitude and a method of precharging by connecting various additional circuits to the data line have been tried. However,
When the signal amplitude of the data line is limited, the operation margin is narrowed, and especially in the case of GaAs-MESFET or the like in which the unevenness of the device characteristics has not been sufficiently solved, the yield decreases, and it is difficult to achieve both high-speed operation and high yield. there were. On the other hand, precharging requires a precharge time, and there is a limit to the speedup.

Therefore, it is an object of the present invention to provide a semiconductor memory circuit which can operate at high speed by shortening the data line charging / discharging time at the time of data reading without lowering the yield.

[0006]

According to the present invention, in a semiconductor memory circuit having a flip-flop circuit formed by using two inverter circuits each including a transistor and a load element, an output terminal of the inverter circuit is connected. In addition, an output transistor in which an electrode corresponding to the state of the inverter circuit based on the signal at the output terminal appears is connected to a data line, a read word line to which a signal for controlling data read is given, and a read word line A driving transistor for driving the output transistor based on a signal of the word line.

[0007]

Since the semiconductor memory circuit according to the present invention is configured as described above, the data line is driven by the output transistor by controlling the output transistor by the signal from the read word line by the drive transistor, A signal corresponding to the state of the inverter circuit will appear on the data line.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory circuit according to an embodiment of the present invention will be described below with reference to FIG. 1 of the accompanying drawings.

Also in this semiconductor memory, two inverter circuits are connected in which FETs 21 and 23 whose gate and source are short-circuited are used as loads and FETs 22 and 24 whose drains are connected to the loads are used as input transistors. A flip-flop circuit is a basic component. FET
Transfer gates 25 and 26 connect the data lines Y and Y to the output terminals (points) A and B of the inverter circuit according to the voltage applied to the write word line X _W. The voltage V _SS is applied to the sources of the FETs 22 and 24.

In this embodiment, the output transistor F is used.
ET1 and ET2 are provided. The FETs 1 and 2 have gates connected to the output terminals (points) B and A of each inverter circuit, and drains connected to the data lines Y and Y, respectively. Furthermore, a read-only read word line X
_R is provided. An FET in which the read word line X _R is connected to the gate and the drain is an output transistor
An FET3, which is a drive transistor connected to the sources 1 and 2 and having a voltage V _SS applied to the sources, is provided.

In such a semiconductor memory circuit, in order to write data, a high level voltage is applied to the write word line X _W to form a transfer gate F.
The ETs 25 and 26 are made conductive, and signals corresponding to the states to be written to the data lines Y and Y are given. On the other hand, in order to read data, a high level voltage is applied to the read word line X _R. Then, the FET3, which is a drive transistor, becomes conductive, and the FETs 1 and 2 become operable. Here, assuming that the potential of the output terminal B of the inverter circuit whose load is the FET 21 is high level and the potential of the output terminal A of the inverter circuit whose load is the FET 23 is low level, the FET 1 becomes conductive and the FET
2 is in the cutoff state. As a result, a low level voltage appears on the data line Y and a high level voltage appears on the data line Y.

As described above, in this embodiment, since the data lines Y and Y are driven by the FETs 1 and 2 which are output transistors at the time of reading data, the data line is conventionally charged and discharged with a small amount of charge in the memory cell. Charge and discharge are performed at a higher speed than the circuit, and high-speed operation is ensured.

In the embodiment, since the number of transistors and the number of signal lines increase, the area of the unit memory cell increases, but high speed operation is required even with a relatively small memory capacity. It is optimum in a field, for example, a register file used inside the CPU.

[0014]

As described above, according to the present invention,
When reading data, the output line is driven by the output transistor driven by the drive transistor, so the charge and discharge of the data line are performed with a charge having a much larger capacity than the charge in the conventional memory cell. Enables high speed operation.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional semiconductor memory circuit.

[Explanation of symbols]

1, 2 ... FET (output transistor) 3 ... FET (driving transistor) 21, 23 ... FET (load) 22, 24 ... FET (input transistor) 25, 26 ... FET (transfer gate) X _R ... Read word line X _W … Write word line Y, Y … Data line

Claims (1)

Claim: What is claimed is: 1. A semiconductor memory circuit having a flip-flop circuit formed by using two inverter circuits each including a transistor and a load element, wherein an output terminal of the inverter circuit is connected. Also, an output transistor having an electrode connected to a data line, in which a signal corresponding to the state of the inverter circuit appears based on the signal at the output end, a read word line to which a signal for controlling data read is provided, and the read word A semiconductor memory circuit, comprising: a drive transistor that drives the output transistor based on a line signal.