JPH0352899U - - Google Patents
Info
- Publication number
- JPH0352899U JPH0352899U JP11265689U JP11265689U JPH0352899U JP H0352899 U JPH0352899 U JP H0352899U JP 11265689 U JP11265689 U JP 11265689U JP 11265689 U JP11265689 U JP 11265689U JP H0352899 U JPH0352899 U JP H0352899U
- Authority
- JP
- Japan
- Prior art keywords
- data
- shift register
- output
- circuit
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of Gas Discharge Display Tubes (AREA)
Description
第１図はこの考案の一実施例のシフトレジスタ
の回路図、第２図は一実施例の状態説明図、第３
図は第２実施例のシフトレジスタの回路図、第４
図は第２実施例の状態説明図である。第５図は、
シフトレジスタ回路で駆動させる出力ドライバを
使用した例を示すプラズマ・デイスプレイ・パネ
ルのブロツク図、第６図は従来のシフトレジスタ
の回路図、第７図は従来のシフトレジスタ回路の
状態説明図である。
９……出力選択回路、１０……リセツト回路。
Fig. 1 is a circuit diagram of a shift register according to an embodiment of this invention, Fig. 2 is an explanatory diagram of the state of an embodiment, and Fig.
The figure is a circuit diagram of the shift register of the second embodiment.
The figure is a state explanatory diagram of the second embodiment. Figure 5 shows
A block diagram of a plasma display panel showing an example of using an output driver driven by a shift register circuit, FIG. 6 is a circuit diagram of a conventional shift register, and FIG. 7 is an explanatory diagram of the state of a conventional shift register circuit. . 9... Output selection circuit, 10... Reset circuit.
Claims (1)
へシフトするシフトレジスタ回路において、 これらのシフトレジスタ群に取り込まれている
データパルスのうち先頭データパルスの存在する
ブロツクの並列データ出力のみパルスを出力させ
る出力選択回路と、 シフトレジスタ群の直列データ出力より出力さ
れるデータパルスにより、シフトレジスタ群に取
り込まれているデータ以外のパルスをすべてクリ
アさせるリセツト回路を有することを特徴とする
シフトレジスタ回路。[Claims for Utility Model Registration] In a shift register circuit that takes in data and shifts this data from the previous stage to the next stage, a block in which the leading data pulse exists among the data pulses taken into these shift register groups is parallelized. It is characterized by having an output selection circuit that outputs a pulse only for data output, and a reset circuit that clears all pulses other than the data taken into the shift register group by the data pulse output from the serial data output of the shift register group. Shift register circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11265689U JP2511408Y2 (en) | 1989-09-26 | 1989-09-26 | Shift register circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11265689U JP2511408Y2 (en) | 1989-09-26 | 1989-09-26 | Shift register circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0352899U true JPH0352899U (en) | 1991-05-22 |
| JP2511408Y2 JP2511408Y2 (en) | 1996-09-25 |
Family
ID=31661099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11265689U Expired - Lifetime JP2511408Y2 (en) | 1989-09-26 | 1989-09-26 | Shift register circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2511408Y2 (en) |
-
1989
- 1989-09-26 JP JP11265689U patent/JP2511408Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2511408Y2 (en) | 1996-09-25 |
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