JPS62145221A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To prevent an unnecessary part from being displayed by mistake even if a timing signal has distortion by providing an interrupt period at the boundary between adjacent timing signals. CONSTITUTION:A timing control circuit 7 controls timing signals to provide the constant interrupt period at the boundary between timing signals which adjoin to each other with time. A control circuit 1 sends out the timing signals from a terminal 1a and also generates an interrupt signal which continues from a time tau before the rising point of the signal to the rising point of the signal. Consequently, the interrupt period tau is obtained between adjacent timing signals which are transmitted to a common driver actually. This interrupt period tauis set to such a value that even if distortion is present finally on a liquid crystal common line like a rounded waveform shown by a dotted line, the distortion is absorbed sufficiently.

Description

[Detailed description of the invention] This invention relates to a liquid crystal drive circuit.

[Conventional technology]

Conventionally, when time-divisionally driven display is performed on a liquid crystal display device, a circuit as shown in FIG. 3 is often used.

In the figure, 1 is a control circuit, 2 is a timing signal generation circuit, 3 is a common driver that converts the timing signal into a liquid crystal display signal and outputs it, 4 is a column data generation circuit, and 5 is a column data converter that converts the column data into a liquid crystal display signal and outputs it. 6 is a liquid crystal display device.

Next, this operation will be explained. For example, according to the clock signal φ from the 91st, the common line (n-2) of the liquid crystal display element 6, (
A timing signal is generated to sequentially designate n l), . . . (n+2). Generally, this timing signal generation circuit is composed of a shift register, etc., and often shifts data of "1" as shown in FIG. It is stored separately on common lines, and necessary display data is generated for the line designated at that time in accordance with the generation of a timing signal. Generally, the column data generation circuit is
It consists of a ROM that stores display data, a shift register that sequentially takes out data from the ROM, and a latch.

When the control circuit 1 sends a signal to each driver 3.5 to synchronize each of these data, each driver
Each data is converted into a voltage waveform necessary for display and output to the liquid crystal display element 6. Then, only a specific line of the matrix of liquid crystal cells specified by the timing signal is displayed.

[Problem that the invention seeks to solve]

As described above, the conventional time-division type liquid crystal drive circuit outputs temporally adjacent timing signals, so if the voltage waveform appearing on the common line of the liquid crystal display element is distorted due to the stray capacitance of the liquid crystal, for example, As shown in Figure 8 Φ), (n
When the +1)th timing signal is applied, the nth timing signal still remains as shown in FIG. 8 (IL). Then, as shown in Figure 9, (n+ 1
), or some data is also displayed on the nth line. In the conventional example, when such a phenomenon becomes severe, correct display cannot be performed.

This invention was made to solve the above-mentioned problems, and even if the voltage waveform applied to the electrodes of the liquid crystal is slightly distorted due to the stray capacitance of the liquid crystal, incorrect data will be displayed on other liquid crystal cells. The purpose of this invention is to obtain a time-division type liquid crystal drive circuit that is free from noise.

[Means for solving problems]

The present invention is provided with means for providing an interwoven period at the boundary between temporally adjacent timing signals.

[For production]

The portion of the timing signal whose waveform is distorted is prohibited from being displayed during the interwoven period.

[Embodiments of the invention]

FIG. 1 is a block diagram showing one embodiment of the present invention,
The same symbols are used for the same parts as in FIG. 6.

In FIG. 1, T is a timing control circuit that controls timing signals and provides a constant interrupt period at the boundaries of temporally adjacent timing signals. The control circuit sends out a timing signal as shown in FIG. 7 from the terminal 1a, and continues from a time τ before the rising edge of the signal until the rising edge of the signal as shown in FIG. 3(e).
In FIG. 1, the basic operating principle is the same as that of the conventional example shown in FIG. 6, which generates the interrupter signal shown in FIG. Therefore, the timing signal generation port jI2I2, which becomes a timing signal, sequentially connects each common line of the liquid crystal matrix as shown in FIG. 9, for example. lk, generates a specified timing signal. Further, the column data generation circuit 4 outputs data to be displayed on each common line according to the timing of this timing signal. Then, according to the control signal from the control circuit 1, these data are transmitted to the common driver 3. The signals are simultaneously transmitted to the column driver 5.

Here, the timing signal, which is a common signal, is transmitted to the common driver 3 through the timing control circuit 7.

This timing control circuit T can be realized by a simple circuit as shown in FIG. 2, for example. This circuit converts the timing waveforms shown in FIGS. 3(a) and 3(b) sent from the timing generation circuit to the timing waveforms shown in FIG. 3(d) using the interrupter signals shown in FIG. 3(c).

Shape the waveform as shown in ←). Therefore, there is a third signal between adjacent timing signals actually transmitted to the common driver.
As shown in Figures (d) and (e), there is an interrupt period of τ. This interwoven period τ is set to a value that can sufficiently absorb even if distortion ultimately exists in the liquid crystal common line, as shown by the distorted waveforms shown by the dotted lines in Figure 3(d) and (e). .

As described above, the timing signal is controlled as shown in Fig. 3@).

By providing an interval between temporally adjacent signals as shown in (e), even if the timing signal waveform is distorted at the liquid crystal electrode, the signal will not remain until the next common line display timing. This prevents data that should originally be displayed on the next common line from being erroneously displayed on that line.

In the above embodiment, the timing control circuit 7 in FIG. 1 was replaced with the circuit shown in FIG. 2, but any other circuit may be used, and the timing control circuit 7 in FIG. If the circuit configuration outputs the output as shown in FIG.

For example, even with the circuit shown in FIG. 4, it is possible to shape the waveform of the timing signal as shown in FIG. This circuit reduces the width of an input signal by performing a logical AND operation using a generally well-known pulse shaping circuit that uses delay.

〔Effect of the invention〕

As described above, the present invention provides an interwoven period at the boundary between adjacent timing signals, so that even if the timing signal is distorted, unnecessary portions will not be erroneously displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a liquid crystal drive circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the timing control circuit in FIG. 1, FIG. 3 is a waveform diagram of each part in FIG. 2, and FIG.
FIG. 5 is a circuit diagram showing another example of the timing control circuit, FIG. 5 is a waveform diagram of each part thereof, and a waveform diagram of a signal supplied to IN, and FIG. 9 is a diagram showing an example of a conventional display state. 1. Meeting control circuit, 21st timing signal generation circuit,
3...Common driver, 4...Column data generation circuit, 5ΦΦ...Column driver, 6...1 liquid crystal display element, T...Timing control circuit.

Claims (1)

[Claims] 1. A liquid crystal drive circuit that sequentially supplies temporally adjacent timing signals to a liquid crystal element, the liquid crystal drive circuit comprising means for providing an interrupt period at a boundary between adjacent timing signals.