JPH0353661B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of controlling a disk cache device, and particularly to a method of controlling a disk cache device suitable for use in a system requiring high responsiveness.

[Background of the invention]

The disk cache device has the following two functions. The first function is to shorten the average response time for CPU access to disk memory while exchanging data between the CPU and disk memory. Second, by specifying an area on the disk memory and controlling the data in that area so that it always exists on the cache memory, a high-speed response is guaranteed for access to the specified area. This is a function to

On the other hand, a disk cache device can be structurally separated into a control device and a cache memory, but the hardware required for the cache memory is the currently available 64 kilobytes, assuming a memory capacity of 4 megabytes. Even if bit memory is used, 500 ICs are required for data alone, and approximately 1,000 ICs are required if the reliability circuit (RAS) and other peripheral circuits are included.
That is, since a large number of ICs are used, reliability of the device becomes a problem.

In a disk cache device, data in the cache memory is managed in units of blocks of a certain size, but in conventional disk cache devices, a block in which a failure has been detected is not accessed. was dealing with the problem. However, with this method, the second function of the disk cache device mentioned above, that is, when data in a specific area on the disk memory is always retained, if a failure occurs in the storage area of the cache memory, the high-speed It becomes impossible to guarantee a response. In addition, if such a failure occurs, a possible recovery method is to move the entire storage area in the cache memory, but in this case all the data that should be retained will be lost, resulting in a drop in performance. The impact of this is significant. Also, depending on the relationship between the size of the storage area and the location of the failure (block number),
Movement itself may be impossible. Moreover, as mentioned above, disk cache devices handle a large amount of
Since ICs are used, the probability of such a situation occurring is not low.

[Purpose of the invention]

The present invention was developed in view of the above-mentioned shortcomings of the prior art, and when a failure occurs in the area that always holds specific data on the cache memory, it is possible to immediately recover the area and quickly store the specific data. The object of the present invention is to provide a method for controlling a disk cache device that guarantees a response.

[Summary of the invention]

The method of controlling the disk cache device of the present invention is as follows. That is, the data stored in the disk memory includes data in the bind control area, which is not rewritten once it is stored in the cache memory, and data in the LRU control area, which is rewritten. The cache memory stores data in units called blocks, but if a failure occurs in a block that stores data in the bind control area, the block that stores data in the LRU control area is immediately transferred to the bind control area. The system is changed to a block that stores data, recovers the system, and enables high-speed response.

Specifically, blocks that record data in the bind control area are ordered in advance in the order of data addresses on the disk memory, and similarly blocks that store data in the LRU control area are ordered in the order in which data is accessed by the CPU on the cache memory. put. If a failure occurs in a block that stores data in the bind control area, the block is separated from the above ordering. Similarly, the required capacity of a block that stores data in the LRU control area is separated from the above relationship according to a certain standard. Next, the blocks that store data in the separated LRU control area are ordered as new blocks that store data in the bind control area.

[Embodiments of the invention]

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing one embodiment of a disk cache apparatus for carrying out the method of the present invention.
In the same figure, the CPU 100 is the disk memory 2
00 through a control device 300, and the control device 300 has cache memories 400, 500, 6.
00,700. The CPU 100 and the control device 300 are connected by a signal line 10 and a control line 30, and the disk memory 200 and the control device 3
00 is connected by a signal line 20 and a control line 40. Control device 300 and each cache memory 4
00 to 700 are connected by a control signal bus 50, a data bus 60, and an address bus 70.

Disk memory 200 has a storage capacity of 100 megabytes. Further, each of the cache memories 400 to 700 is constituted by an independent board, and each has a storage capacity of 1 megabyte.

FIG. 2a shows the storage area of the disk memory 200, and FIG. 2b shows the storage area of the cache memory 400 to 7.
00 storage area, and FIG. 2c shows the storage area of the controller 30.
It shows the directory within 0. In the cache memory device shown in FIG. 1, the cache memories 400 to 700 manage data in units called blocks.If one unit of this block is 8 kilobytes, the cache memories 400 to 700
There are 512 blocks in the 4 megabyte cache memory. Therefore, originally the cache memory shown in FIG.
There are actually 512 blocks, and the directory shown in FIG. 2c stores 512 pieces of management information corresponding to the 512 blocks. However, as shown in FIGS. 2a, b, and c, in this embodiment, for simplicity, the number of blocks in the cache memory is set to eight (blocks a to h), and the number of directories is changed accordingly. The number is 8.

Directories 1 to 8 are as shown in Figure 2c.
The cache memory 40 consists of a part that stores the block numbers a to h of the blocks to be managed, and a pointer that indicates the number of each directory 1 to 8.
Manage corresponding blocks from 0 to 700.

As shown in FIG. 2a, once the storage area of the disk memory 200 is
Bind control area that will not be rewritten once stored in 00 and cache memory 400 to 7 as many times as desired.
There is an LRU control area that is rewritten on 00. The data in the bind control area stored in the cache memories 400-700 is managed by directories 1-3, and the pointer of each directory 1-3 points to the disk memory of the data stored in the cache memories 400-700. Address order within 200 (smaller address first)
shows. The LRU control area data stored in cache memories 400 to 700 is stored in directory 4.
-8, and the pointers of each directory 4-8 indicate the order in which data stored in the cache memories 400-700 were accessed. That is, the pointers for directories 1-3 indicate the order of addresses on disk memory 200 of the data in managed cache memories 400-700 in relation to the order of directories 1-3.
Further, the pointers for directories 4-8 indicate the access order of data in managed cache memories 400-700 in terms of the order relationship of directories 4-8.

In this embodiment, for the sake of simplicity, it is assumed that the pointers in directories 1 to 8 indicate an order relationship in only one direction. Also, directories 1 to 8 are 2
In the embodiment shown in FIG. 2c, 2
×8=16 words are required. However, in reality, as mentioned above, there are 512 blocks corresponding to 512 blocks.
directories are required, so 2×512
= 1024 words are required. Further, the directories 1 to 8 are provided in the control device 300 because high-speed operation is required.

When a data read command is output from the CPU 100 shown in FIG.
700, the data is transferred from the cache memories 400 to 700, and if the data does not exist, the data is transferred from the disk memory 200 to the CPU 100, and the data is transferred from the cache memories 400 to 700. Write this data into one block. When writing new data to the cache memories 400 to 700, for the data in the LRU control area,
It is desirable to write to the oldest accessed block in the cache memories 400-700. In this embodiment, this is achieved by
The above-mentioned directories 4 to 8 are related by pointers.

FIG. 3 is a diagram showing the structure of directories 1 to 8. As shown in the figure, the directory is composed of two words, and the first word is written with the block number on the cache memories 400-700 in which data managed by the directory is written. In addition to the pointers (7th to 16th bits) indicating the order relationship between directories 1 to 8, the second word includes a plurality of bits for writing various information. 1st word of 2nd word
Bit DE is a bit that indicates that the data managed by the directory is valid.
Indicates that it is valid when DE is “1”. or,
The second bit BB indicates the cache memory 40 in which data managed by the directory is written.
This bit indicates that there is a fault in the block above 0 to 700. When bit BB is "1", it indicates that there is a fault. The fourth bit BND is a bit that indicates whether the data managed by the directory is data in the bind control area or data in the LRU control area. When bit BND is "1", it indicates that the data is in the bind control area; 0'' indicates data in the LRU control area.

4a, b, and c are diagrams showing the storage area of disk memory 200, the storage area of cache memories 400-700, and the contents of directories 4-8 when managing data in the LRU control area. As shown in Figure 4a, data D, E,
F, B, and C are stored in the disk memory 200, and these data are stored in the blocks d, B, and C in the cache memories 400 to 700, as shown in FIG. 4B.
Suppose that they are stored in e, f, g, and h. Now, the data in cache memory 400-700 is F,
Assuming that E, D, C, and B are accessed in the order, directory 5 (new) is accessed as shown in Figure 4c.
The access order of data B to F is maintained by the series of pointer instructions →4 →6 →7 →8 (old). In addition, the pointer LTOP shown in Figure 4c
is a pointer indicating the directory number that manages the data of the disk address most recently accessed in the LRU control area; in this embodiment, it indicates directory 5. In addition, the pointer LBOTTOM shown in Fig. 4c is
This is a pointer that indicates the directory number that manages the data of the disk address that was accessed oldest in the LRU control area, and in this embodiment, it indicates directory 8. And pointers LTOP and XBOTTOM are both control device 3.
00.

When a read command for any one of data C, D, E, and F is output from the CPU 100 and the relationship between data C, D, E, and F is changed,
Then, a command to read data stored in the LRU control area other than data C, D, E, and F is output from the CPU 100, and the cache memory 400 to
If it becomes necessary to rewrite the data on 700, it is possible to express a new old-new relationship by rewriting the pointers of directories 4 to 8.

In this embodiment, it is assumed that there is no failure in each of the blocks d to h of the cache memories 400 to 700 shown in FIG. 1, and that the data B to F are all valid.
Therefore, bits DE of directories 4 to 8 shown in FIG. 3 become "1" and bit BB becomes "0". Also,
Since directories 4 to 8 perform LRU control, bit BND shown in FIG. 3 is "0".

Figure 5 a, b, and c show the disk memory 2 when managing data stored in the bind control area.
00 storage area and cache memory 400 to 7
2 is a diagram showing the storage area of 00 and the contents of directories 1 to 3. FIG. As mentioned above, disk memory 2
Bind control area data Y, Z, W on 00
Once stored in blocks a, b, and c of the cache memories 400-700, they will not be replaced with other data. Generally, the memory capacity of the bind control area on the disk memory 200 is the same as that of the cache memories 400 to 7.
00. Data Y, Z, and W in the bind control area are stored in blocks a, b, and c of cache memories 400 to 700, as shown in FIG. 5b.
is written in. Directories 1 to 3 that manage data Y, Z, and W stored in blocks a, b, and c are the same as directories 4 to 8 in the LRU control area described above, but the bits shown in FIG.
The fact that BND is "1" and the meaning of the directory pointed to by each pointer are different. That is,
As mentioned above, directories 4 to 8, which manage the data in the LRU control area, indicate the old and new access relationship, but directories 1 to 3, which manage the bind control area, specify the data managed by each directory 1 to 3. The address order in the disk memory 200 (the smaller address comes first) is shown. That is, as shown in Figure 5a, the data in the bind control area is stored in the order of addresses Y, Z, and W, so as shown in Figure 5c, the pointer of directory 1 that manages data Y is is data Z
The pointer of directory 2 points to directory 3 that manages data W, and the pointer of directory 3 points to directory 1. Further, the pointer BTOP shown in FIG. Instruct 1. Further, the pointer BBOTTOM shown in FIG. Instruct 3. Then, the pointers BTOP and BBOTTOM are both controlled by the control device 3.
00.

As described above, since the same storage capacity as the bind control area of the disk memory 200 is secured in the cache memories 400 to 700, the cache memory 400 is It is possible to store data in the blocks above 700 in the order of the addresses in the disk memory 200. However, ordering the data in the bind control area in such an address order means that the cache memories 400 to 400 that store the data in the bind control area
If a failure occurs in blocks a, b, and c in block 700, this is an effective means for recovery.

FIG. 6 is a block diagram showing an example of a control device 300 that executes the disk cache device control method of the present invention. The control device 300 includes a microprocessor 310 that controls internal operations as shown in the figure.
Directory and register LTOP,
RAM 320, CPU interface 330, disk interface 340, memory interface 350 that holds LBOTTOM, BTOP, BBOTTOM and data necessary for control, and two internal buses 360 for communication between each element.
370, an input bus 380 and an output bus 390.

7a, b, and c show the cache memory 400.
700 is a diagram showing the operations of the disk memory 200, cache memories 400-700, and directories 1-8 when performing recovery processing assuming that a failure has occurred in block b of 700. FIG.
Further, FIGS. 8a, b, and c are flowcharts showing the operation contents of the above-mentioned recovery processing.

In normal operating conditions, as described above, blocks a to h of cache memories 400 to 700
As shown in the figure, data Y to F are stored, data Y, Z, and W are data in the bind control area, and data B, C, D, E, and F are data in the LRU control area.

If a failure occurs in block b of the cache memories 400 to 700 and it becomes impossible to store data Z, the cache control device 300 follows the flowchart shown in FIGS. 8a and 8b. Perform the ivy motion. That is, steps S1 to S
3 shows the operation of removing the directory that manages the oldest accessed block in the LRU control area from the relationship by the pointer of directories 4 to 8, and freeing the block managed by the removed directory. That is, step S1
Now register the contents of pointer LBOTTOM
Write to SVDBTM. Here, register
SVDBTM is used to temporarily store information necessary for control, and is shown in Figure 6.
It is provided within the RAM 320. That is, in the examples shown in FIGS. 7a, b, and c, since the content of the pointer LBOTTOM is 8, 8 is written to the register SVDBTM. Next, in step S2, the register
Directory 4 with the same content as SVDBTM
Find the pointer 8 and put the directory number in register LBOTTOM. Figure 7 a, b,
In the example shown in c, the contents of register SVDBTM are 8
, and the directory whose pointer content is 8 is directory 7, so the pointer
Write 7 to LBOTTOM. In step S3, the contents of the pointer LTOP are written to the directory pointer searched in step S2. In the example shown in FIGS. 7a, b, and c, the contents 5 of the pointer LTOP are written to the pointer of the directory 7.
With the above, it is completed that a block that has been accessed one time more recently than the oldest block is associated as the block that has been accessed the oldest.

In steps S4 to S14, among the blocks that manage data in the bind control area, the directory that manages the block in which the failure has occurred is separated from the relationship between directories 1 to 3, and further, in the processing of steps S1 to S3, it is freely separated. This process performs a process of associating the old block with a new one as a block that manages data in the bind control area. That is, in step S4, it is determined whether the faulty block is a block that stores data stored at the smallest address (address of disk memory 200) among the data in the bind control area. If YES, the microprocessor 310 sets the flag TOP to "1" in step S5. Here, the flag TOP is provided in the RAM 320 in the control device 300. This means that if the faulty block stores data that is stored at the smallest address among the addresses in the bind control area, the faulty block is discarded from use and steps S1 to S3 are performed. Since the freed block is used as a block for newly storing data in the bind control area, it is necessary to rewrite the contents of the pointer BTOP. This is a process that temporarily stores this information. In step S6,
Similarly, it is determined whether the faulty block stores data stored at the largest address among the addresses in the bind control area (addresses in the disk memory 200). If YES, the microprocessor 310 sets the flag BOTTOM to "1" in step S7. Here, the flag BOTTOM is provided in the RAM 320 in the control device 300. In this process as well, if the block in which the fault has occurred is a block that stores data stored at the largest address among the addresses in the bind control area, the block in which the fault has occurred is discarded as unused, and the step In order to use the blocks freed in S1 to S3 as new blocks for storing data in the bind control area, the pointer
It becomes necessary to rewrite the contents of BBOTTOM.
This is a process that temporarily stores this information. In the examples shown in FIGS. 7a, b, and c, the block in which the failure occurred is block b, which is neither the upper limit nor the lower limit of the block that stores data in the bind control area, so the flag TOP and flag BOTTOM are set to "1". It is never set.

In step S8, a directory whose pointer contents are equal to the directory number of the block in which the failure has occurred is searched for, and the contents of the register SVDBTM are written to the pointer of the corresponding directory. In the example shown in FIGS. 7a, b, and c, the number of the directory in which the failure has occurred is 2, so directory 1 is selected, and the content 8 of register SVDBTM is written to the pointer of directory 1. As a result, the block b in which the failure has occurred is removed from the relationship of the directory that manages the data in the bind control area, and the directory 8 that manages the block h, which has become free through the processing of steps S1 to S3, is
is associated as a directory that manages data in the bind control area.

In step S9, the contents of the pointer of the directory that manages the failed block are changed to the directory that was associated in step 8 as the directory that manages data in the bind control area (the directory indicated by the contents of register SVDBTM). written to the pointer. In the example shown in FIG.
is written to the pointer of the associated directory 8. Through this process, directory 8 that manages block h is changed from directory 1 to directory 8.
→It means that they are completely related in the order of 3.

In step S10, bit BND of the directory selected in step S8 is set to "1", and bit DE is set to "0".
In the example shown in Figures 7a, b, and c, directory 8
bit BND is set to “1” and bit DE
is set to "0". As a result, the directory 8 has been changed from a directory that manages data in the LRU control area to a directory that manages data in the bind control area.

In step S11, the flag BOTTOM
Determine whether “1” is set to
If “1” is set, step S
Register the contents of pointer BBOTOM at 12
Rewrite to the contents of SVDBTM. Step S13
In this step, it is determined whether the flag TOP is set to "1", and if it is set to "1", the contents of the pointer BTOP are rewritten to the contents of the register SVDBTM in step S14.
In the examples shown in Figures 7a, b, and c, the flag
Since neither BTTOM nor the flag TOP is set to "1", the processes of steps S12 and S14 are not executed. Through the processing in steps S11 to S14, the number of the directory that manages the data stored at the smallest address (address of the disk memory 200) among the data in the bind control area is written to the pointer BTOP,
The number of the directory that manages the data stored at the largest address (address of disk memory 200) will be written to BBOTTOM.

In this embodiment, as a replacement for the defective block,
Although we have shown an example of using the block that was currently accessed the earliest, it is possible to select any block among the blocks that stores data in the LRU control area.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when a failure occurs in the bind control area that always holds specific data on the cache memory, the block in the bind control area where the failure has occurred is replaced by By using a block in the LRU control area, in which data is not rewritten, as a new block in the bind control area, it is possible to immediately recover and guarantee high-speed data response in the specific area.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a disk cache device which is the object of the present invention, FIG. 2a is a diagram showing the storage area of the disk memory shown in FIG. 1, and FIG. 2b
is a diagram showing the storage area of the cache memory shown in FIG. 1, FIG. 2c is a diagram showing a directory in the control device shown in FIG. 1, FIG. 3 is a diagram showing details of the directory, and FIG. is a diagram showing the storage area of the disk memory shown in FIG. 1, FIG. 4b is a diagram showing the storage area of the cache memory shown in FIG. 1, and FIG. 4c is a diagram showing the directory in the control device shown in FIG. 1. FIG. 5a is a diagram showing the storage area of the disk memory shown in FIG. 1, FIG. 5b is a diagram showing the storage area of the cache memory shown in FIG.
FIG. 6 is a block diagram showing details of the control device shown in FIG. 1, and FIG. 7a shows a storage area of the disk memory shown in FIG. 1. FIG. 7b is a diagram showing the storage area of the cache memory shown in FIG. 1, and FIG. 7c is a diagram showing the storage area of the cache memory shown in FIG.
FIGS. 8a and 8b are flowcharts showing the operation of an embodiment of the present invention. 100...CPU, 200...Disk memory, 3
00...Control device, 400-700...Cache memory, C, B, D, E, F, W, Y, Z...Data, a-h...Block, 1-8...Directory.

Claims (1)

[Scope of Claims] 1. In a disk cache device that stores data on a disk memory in a cache memory via a control device and enables high-speed response to data read commands from a CPU, the cache memory comprises: The first step is to order the blocks that store data in the bind control area without data rewriting in the order of data addresses on the disk memory, and rewrite the data on the cache memory.
A block that stores data in the LRU control area
The second step is to order the data accessed by the CPU on the cache memory, and the second step is to separate the faulty block from the ordering in the first step when a fault occurs in a block that stores data in the bind control area. 3, and a fourth step in which, among the blocks that store data in the LRU control area, the least recently accessed block that is ordered lowest in the ordering in the second step is separated from the ordering in the second step. In place of the faulty block that was separated in the third step, a block that stores the data in the LRU control area that was separated in the fourth step is used to store the data in the bind control area in the first step. and a fifth step of newly ordering the blocks to be stored.