JPH0353718A - Plural numerical values counting type counter circuit - Google Patents

Abstract

PURPOSE:To count plural numerical values individually with less circuit scale constitution by using a very less circuit scale memory whose equivalent gate number is nearly 0.1 in place of plural data storage flip-flop circuits employing many flip-flops. CONSTITUTION:A very less circuit scale memory whose equivalent gate number is nearly 0.1 is used in place of plural data storage flip-flop circuits. For example, when 6 kinds of counted values are stored in the memory 2, a counted value AO stored in an address of the memory 2 is read, and inputted to a counting arithmetic circuit 3, where arithmetic calculation or the like is implemented. The outputted counted value BO is written again in the same address of the memory 2. A counted value Al is read and inputted to the counting arithmetic circuit 3, and a counted value Bl calculated and outputted from the counting arithmetic circuit 3 is written again in the memory 2.

Description

[Detailed Description of the Invention] [Summary] To enable a multi-value counting type counter circuit that can individually count multiple values to be able to count multiple values individually with a small circuit scale (number of gates). A memory capable of holding a plurality of counter values, a counting operation circuit that performs necessary counting operations based on the count values held in the memory, and a counter that is to be input from the memory to the counting operation circuit. The device is configured to include a memory control circuit that reads a value from the memory and writes a counter value calculated and outputted by the counting operation circuit to the memory.

[Industrial Application Field] The present invention relates to a multi-value counting type counter circuit that can individually count a plurality of values.

For example, in transmission technology, there are cases where it is desired to extract multiple time slot information from one transmission frame.

In such a case, since a plurality of count values from the beginning of the frame are required, a counter circuit that can individually count the plurality of values is required.

[Prior Art] Fig. 4 is a block diagram showing a conventional example. In Fig. 4, 1-1.1-2.1-N is a counter circuit;
Each counter circuit 1-i (i=1 to N) includes a data holding flip-flip circuit 2-i and an arithmetic circuit 3-i.

Here, the data holding flip-flip circuit 2-1 is
Plural (4) D flip-flops 21i, 2 2
- i, 2 3 - i, 2 4 -
j, and the Q output Q of the D flip-flop 21-i. becomes the output of the first bit l], the Q output Q1 of the D flip-flop 22-i becomes the output of the second bit,
The Q output Q2 of the D flip-flop 23-1 is the output of the third bit, and the Q output Q3 of the D flip-flop 24-i is the output of the fourth bit.

Further, the arithmetic circuit 3-i performs a carry operation or a carry down operation, and is an exclusive OR gate (EX gate).
31-i, 32-it 33-i and AND gate (AN
It is configured as a logic circuit in which D gates 34-i and 35-i are combined as shown in FIG.

With this configuration, each counter circuit 1-i counts up or down each time a clock is input, and outputs the counting result to each output Q0 to Q.
Output as bit output. In the case of up-counting, the output changes as shown below.

roooOJ -4 roo01''-+roo10J
-} "0011" → rQ100J → r0 1 0 1
J→ro 1 1 0J→ro 1 1 1J→rlo
oOJ→rlooIJ→rl O 1 0J→rlo1
1”→rlloOJ-)riioiJ + rll
lOJ -+rl 1 1 1J Then, if you want to capture the 4th and 5th time slot information from the beginning of the frame, for example, take the data where the outputs of the counter circuits 1-1 and 1-2 become "0100J, ro101J". You can incorporate each one.

[Problems to be Solved by the Invention] However, in such conventional counter circuits, in order to count multiple values (add or subtract values by 1), as shown in FIG. Circuit 1-
Since the required number (N) of i must be arranged in parallel,
As the number of counter circuits increases, the circuit scale becomes extremely large.

In particular, when converting into an LSI, each flip-flop requires a gate size of about 10 gates, so conventional circuits that use many flip-flops have the problem of not being suitable for LSI in terms of circuit size. be.

The present invention aims to solve these problems, and provides a multi-value counting type counter circuit that is capable of individually counting multiple values with a small circuit scale (number of gates). The purpose is to

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 2 is a data holding memory, and this memory 2 can hold a plurality of counter values.

3 is a counting operation circuit, and this counting operation circuit 3 is connected to the memory 2.
Necessary counting operations are performed based on the count values held in the .

Reference numeral 4 denotes a memory control circuit, and this memory control circuit 4 reads the counter value to be input from the memory 2 to the counting operation circuit 3 from the memory 2, and also reads out the counter value calculated and output from the counting operation circuit 3 to the memory. This is for writing to 2.

[Function] In the multi-value counting type counter circuit of the present invention described above, the count value held at a certain address in the memory 2 is read out, this is input to the counting operation circuit 3, and the required counting operation is performed. It is done. Then, the counter value calculated and outputted by the counting calculation circuit 3 is written into the memory 2 again.

Next, the count value held at another address in the memory 2 is read out and inputted to the counting operation circuit 3, where the required counting operation is also performed. The counter value that has been output is written to memory 2 again. Then, the above-mentioned processing is performed for the required number of data stored in the memory 2.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, 2 is a data holding memory, and this memory 2 has a continuous memory area that holds a plurality of counter values. As this memory 2, for example, a RAM is used. Here, this memory 2 has an equivalent number of gates of 0.1
It is something that can be constructed with a small circuit scale.

3 is a counting operation circuit, and this counting operation circuit 3 is connected to the memory 2.
It performs a carry operation or a carry down operation based on the count value held in the exclusive OR gate (EX gate) 31, 32, 33, and
ND gate) 34.35 Inversion gate (NOT gate) 3
6 are combined as a logic circuit as shown in FIG.

4 is a memory control circuit, and this memory control circuit 4 inputs the counter value from the memory 2 to the counting operation circuit 3 and outputs the counter value to the output port Q of the memory 2. -QJ is used to read out the counter value calculated by the counting calculation circuit 3 and written through the input ports D0 to D of the memory 2. For this purpose, the memory control circuit 4 includes a write address setting section 41 that sets a write address, a continuous address setting section 42 that sets a read address, a write control section 43 that controls writing to the memory 2, and a memory control section 43 that controls writing to the memory 2. A readout control unit 44 is provided for controlling readout from 2.

Incidentally, a clock is inputted to the memory 2 and the memory control circuit 4 to set the write/read timing as shown in FIG. 3(a). The clock speed in this case is, for example, 6 Mbit/see to 20 Mb.
It/see (this speed is lower than the clock speed used for software processing) is used.

With the above configuration, for example, if six types of count values are held in the memory 2, the count value AO held at a certain address in the memory 2 is first read out,
This is input to the counting operation circuit 3, where the above-mentioned carry operation and the like are performed. After that, this counting operation circuit 3
The counter value BO calculated and output is written to the same address in the memory 2 again.

Next, the count value A1 held at another address in the memory 2 is read out and inputted to the counting operation circuit 3, whereupon the above-mentioned required counting operation is also performed. The calculated and outputted counter value B1 is written into the memory 2 again.

Then, the above processing is performed for the required number (6>) held in the memory 2.

The time charts at this time are shown in Figures 3(a) to (
c).

In this way, the memory 2, which has a very small circuit size with an equivalent gate number of about 0.1, is used instead of multiple data retention flip-flop circuits (each data retention circuit uses many flip-flops). Moreover, since the counting operation circuit is shared, it is possible to provide a counter circuit that can individually count a plurality of values with a small circuit scale (number of gates).

Although the above embodiment has been described using a 4-bit output counter circuit as an example, it goes without saying that the present invention can be similarly applied to other bit output counter circuits.

[Effects of the Invention] As detailed above, according to the multi-value counting type counter circuit of the present invention, the memory has a very small circuit scale with an equivalent number of gates of about 0.1, and uses many flip-flops. This counter circuit is used in place of multiple data holding flip-flop circuits, and since the counting operation circuit is shared, it has a small circuit configuration and can count multiple values individually. It has the advantage of being able to provide

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a time chart of the present multi-value counting type counter circuit, and Fig. 4 is a block diagram showing a conventional example. It is a diagram. In the figure, 2 is a memory, 3 is a counting circuit, 4 is a memory control circuit, 31 to 33 are exclusive OR gates, 34 and 35 are AND gates, 36 is an inversion gate, 41 is a write address setting section, 42 43 is a write control unit; and 44 is a continuation control unit.

Claims (1)

[Claims] A memory (2) that can hold a plurality of counter values, a counting operation circuit (3) that performs necessary counting operations based on the count values held in the memory (2); The counter value to be input from the memory (2) to the counting operation circuit (3) is read from the memory (2), and the counter value calculated and output by the counting operation circuit (3) is read out from the memory (2). 1. A multi-value counting type counter circuit comprising: a memory control circuit (4) for writing data into a memory control circuit (4).