JPH0353719A - A/d converter - Google Patents

Abstract

PURPOSE:To optimize the clock delay quantity by allowing a parallel sub A/D converter circuit to operate a noise detection circuit in a control circuit for the reset period of a successive approximation main A/D converter section. CONSTITUTION:A main A/D converter section 7 receives an analog signal inputted from an input terminal 1 and selected by an analog multiplexer in a control circuit 4 as an analog input 9. The operation of the main A/D converter section 7 is controlled by a main control signal 11 and a digital signal subjected to A/D conversion is outputted from a main digital output 12 to the control circuit 4. A noise detection circuit 5 receives a digital signal 14 sent from a sub A/D converter section 8 and A/D-converted for the reset period of the main A/D converter section 7 and detects and stores the delay of a clock delay circuit 6 minimizing the noise level. The operation of the main A/D converter section 7 is started by using the delay quantity as a detection value.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an A/D converter, and particularly to an A/D converter that is integrated on the same substrate as a large-scale control circuit using semiconductor integrated circuit technology. Concerning vessels.

[Conventional technology]

Conventionally, such large-scale control circuits, such as 8-bit or 1
An example of integrating an A/D converter on the same board as a circuit such as a 6-bit microcomputer is the NE
C Technical Report VoJ2.39N [L10・1986・PP75
A successive approximation type A/D converter having an eight-man multiplexer is known, as shown in the "CMOS 8-bit single-chip microcomputer μPD78112" published in Japan. The conversion time of such an A/D converter is 26.7μ
sec.

[Problem to be solved by the invention]

Since the conventional A/D converter mentioned above has a large-scale control circuit on the same substrate, the digital noise generated from this control circuit increases with the miniaturization of process technology.
This is a factor that deteriorates the performance of the D converter.

For information on how much noise is generated, please refer to “DESIG
N OF MOS VLSI CIR-CUI
TS FOR TELECOMMUNI-CA
TIONS” Prentice-Ha
1Inc. 1985-PP321-324, which states that when 8-bit output buffers operate simultaneously, a current of about 25 mA flows, and when the lead inductance is 50 nH, a current of about 25 mA flows in the power supply line.
A noise of 50mV is generated. Noise generated in such power supply lines increases with the miniaturization of process technology. On the other hand, miniaturization of process technology leads to improvement in the driving ability of the MOS transistors used. As a result, a large amount of power supply noise is generated at the internal gates. Therefore, let us consider the case where this power supply noise occurs during the period when the reference voltage of the A/D converter and the input voltage are compared. for example,
When this power supply noise occurs on the ground line, the reference voltage changes and the error of the A/D converter increases. In addition, when noise occurs in the power supply, false judgments may be output if the power supply noise rejection ratio of the comparator used to compare the reference voltage and input voltage is insufficient. Conventionally, as a countermeasure against these power supply noises, (1) the power supply wiring is separated between the control circuit and the A/D converter.

■Prevent noise induction by terminating the substrate potential and well potential to the power supply line with low impedance.

■Improve the power supply noise rejection ratio by making the A/D converter fully differential.

Methods such as these are used. However, there are problems such as deterioration of noise resistance due to an increase in the high frequency range of the noise spectrum as the evening lock speed increases, an increase in noise power due to an increase in the scale of integrated circuits, and a demand for higher integration of A/D converters. A point is left. [Means for Solving the Problems] An A/D converter of the present invention includes a control circuit having a noise detection circuit and a clock delay circuit, a successive approximation type main A/D conversion section both connected to the control circuit, and a control circuit having a noise detection circuit and a clock delay circuit. a parallel sub-A/D converter, and a tfl4 command is provided to cause the parallel sub-A/D converter to operate a noise detection circuit of the control circuit during a reset period of the successive approximation main A/D converter. Ru.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an A/D converter showing an embodiment of the present invention.

As shown in FIG. 1, this embodiment has an analog input terminal (
IN^) 1, a control circuit 4 connected to a digital input/output terminal (I/O) 2 and a clock terminal 3, and having a noise detection circuit 5 and a clock delay circuit 6;
The main A/D converter 7 receives an analog input 9, an A/D operating clock 10, and a main control signal 11 from the main A/D converter 7, and sends out a main digital output 12. Operating clock 10. Sub control signal 1
3 and outputs a sub digital output 14. The analog input terminal 1 described above becomes a plurality of terminals when an analog multiplexer (not shown) is provided in the control circuit 4. In addition, digital input/output terminal (I/O) 2 is shown as a representative, and a plurality of terminals including a digital input terminal and a digital output terminal are displayed. It will be done. Further, the clock terminal 3 represents the operation clock input terminal of the control circuit 4, and becomes unnecessary when an oscillation circuit using a crystal oscillator or the like is provided on the integrated circuit. The clock input from this clock terminal 3 is used by the control circuit 4 to connect the main and sub A/Ds.
It is converted as an operating clock for converters 7 and 8 and supplied via clock delay circuit 6, respectively.

In this A/D converter, the main A/D converter 7 inputs, as an analog input 9, an analog signal input from an analog input terminal 1 selected by an analog multiplexer (not shown) in the control circuit 4. Above this A/D
The operation of the converter 7 is controlled by a main control signal 11,
The A/D converted digital signal is the main digital output 1.
2 to the control circuit 4. This A/D converted digital signal is output from the control circuit 4 to the outside from the digital input/output terminal 2 as required.

Further, the sub A/D converter 8 also operates in the same manner as the main A/D converter 7, and its operation is controlled by the sub control signal 13.
The D-converted digital signal is output from the sub digital output 14 to the control circuit 4.

On the other hand, the noise detection circuit 5 receives from the control circuit 4 the A/D-converted digital signal 14 sent from the sub-A/D converter 8 during the reset period of the main A/D converter 7, and detects the minimum noise level. It has a function of detecting and storing the amount of delay of the clock delay circuit 6.

Next, the specific operation of such an A/D converter will be explained.

■First, an A/D conversion command is input to the control circuit 4. This A/D conversion command may be input from the outside via the digital input/output terminal 2 or from a program incorporated in the control circuit 4, but the operation is the same in either case.

■Next, the main A/D converter 7 is reset. ■Next, connect the analog human power 9 to the ground potential.

(2) Also, set the delay amount of the clock delay circuit 6 to A.

(2) Also, the sub A/D converter 8 is operated, and the conversion result is inputted from the sub digital output 14 via the control circuit 4 to the noise detection circuit 5 and stored therein. ■Next, the delay amount of the clock delay circuit 6 is determined as B, C,...
, and repeat steps ■ and ■ above.

■When the delay amount of this clock delay circuit 6 is completed,
The amount of delay at which the amount of noise in the sub A/D converter 8 stored in the noise detection circuit 5 is minimized is detected. (2) Further, the operation of the main A/D converter 7 is started using the delay amount of the clock delay circuit 6 as a detected value.

In this way, the amount of delay of the clock delay circuit 6 is set so that the noise of the control circuit 4 is minimized during the reset period before the main A/D converter 7 starts operating.

FIG. 2 is a diagram of the clock delay circuit shown in FIG. 1.

As shown in FIG. 2, the clock delay circuit 6 receives an operating clock from a clock terminal via a buffer (not shown).
It consists of a transfer gate 16 at each output.
is connected. Note that the control leads for driving the transfer gate 16 are omitted because they are not directly related to the present invention.

For example, if the delay amount of the inverter is 2 nsec per stage, the delay amount of this delay circuit 6 is Onsec, 4 nsec.
It is possible to select between c, 8 nsec, and 16 nsec. Further, the number of inverter stages can be any number, and the required delay step and delay range can be selected. Furthermore, when outputting the A/D operation clock 10 from the transfer gate 16, it is preferable to provide a buffer at a stage subsequent to the transfer gate 16 when the wiring is long.

FIG. 3 is a more specific circuit diagram of the main/sub A/D converter in FIG. 1.

As shown in FIG. 3, the main A/D converter 7 has a reference voltage 17
It has a comparator 20 connected via a unit resistor 18 that divides the voltage and a transfer gate 19 that takes out the divided voltage, and the other input of this comparator 20 is connected to an analog human power 21. Furthermore, the A/D converter 7 has a successive approximation type circuit structure as described above.

On the other hand, the sub A/D converter 8 shares a reference voltage 17 and a unit resistor 18 with the main A/D converter 7. The voltage divided by this unit resistor 18 is directly supplied to four comparators 22 and compared with the other analog power 21, respectively. still,
As described above, this sub-A/D converter 8 has a parallel circuit configuration to increase the speed. In other words, since it is necessary to perform A/D conversion as many times as the number of delay steps during the reset period of the main A/D converter 7, a successive approximation type circuit configuration eliminates the drawback that the reset period becomes longer. It's for a reason.

Although the comparison output of the auxiliary A/D converter 8 in FIG. 3 is in the form of a bar thermometer, it may also be converted into a pinary code by installing a simple logic circuit after the comparator.

Similar to FIG. 3, FIG. 4 is a circuit diagram of the main/sub A/D converter in FIG. 1.

As shown in FIG. 4, this circuit differs from the previous embodiment in that the resolution of the sub A/D converter 8 is changed to twice that of the main A/D converter 7. That is, in FIG. 4, the main A/D converter 7 extracts every two unit resistors 18 using the transfer gate 19 and supplies them to one input of the comparator 20, and supplies them to the other input of the comparator 20. I am trying to compare it with analog human power 21. Also, sub-A/D
The converter 8 takes out the divided voltage for each unit resistor 18 and supplies it to the comparator 23 ifi. In order to simplify the diagram, four comparators are shown in one block. The internal configuration and connections of this comparator 23 are shown in FIG.
It is the same parallel type as 2.

In this way, by doubling the resolution of the sub A/D converter 8, a clock delay amount with less noise can be selected. Note that the resolution of this sub A/D converter 8 can be selected to be an integral multiple or an integer fraction of that of the main A/D converter 7, and the resolution and clock delay amount of the main A/D converter 7 can be selected. It is necessary to consider and make a selection.

In the above-described embodiment, the resistor string is used as the main/sub A/D converter, but the present invention can be applied similarly even if the main/sub A/D converter is configured by combining a capacitor array and a resistor string. can be carried out.

〔Effect of the invention〕

As explained above, the A/D converter of the present invention includes a control circuit having a noise detection circuit and a clock delay circuit, a successive approximation type main A/D conversion section and a parallel type sub-A/D conversion section both connected to the control circuit. The amount of clock delay can be reduced by providing an A/D conversion section and operating the noise detection circuit of the control circuit from the parallel sub A/D conversion circuit during the reset period of the successive approximation type main A/D conversion section. In addition to making optimization possible, this has the effect of minimizing the influence of power supply noise generated from large-scale control circuits and output buffers, and achieving higher accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an A/D converter showing an embodiment of the present invention, FIG. 2 is a clock delay circuit diagram shown in FIG. 1, and FIG.
This figure is a circuit diagram of the main/sub A/D converter in FIG. 1, and FIG. 4 is a circuit diagram of the main/sub A/D converter in FIG. 1, similar to FIG. 3. 1... Analog input terminal (INA), 2... Digital input/output terminal (I/O>, 3... Clock terminal, 4
...Control circuit, 5...Noise detection circuit, 6...Clock delay circuit, 7...Main A/D conversion section, 8...Sub-A
/D conversion section, 9, 21...analog input, 10...
A/D operation clock, 11... Main control signal, 12...
・Main digital output, 13...Sub control signal, 14...
・Sub digital output, 15...Delay element, 16.19
...Transfer gate, 1 7...Reference voltage (terminal) 1 8...Unit resistance, 20, 2 2...Comparator, 2 3...4 comparators.

Claims (1)

[Claims] a control circuit having a noise detection circuit and a clock delay circuit; and a successive approximation type main A/D connected to the control circuit.
A conversion section and a parallel sub A/D conversion section are provided, and the parallel sub A/D conversion section is provided during a reset period of the successive approximation type main A/D conversion section.
An A/D converter, characterized in that a noise detection circuit of the control circuit is operated from a D conversion section.