JPH0353773B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing an FET made of a compound semiconductor. Previously, FETs made of GaAs had the structure shown in Figure 1. i.e. chrome (Cr)
A mesa-shaped active layer 2 made of n-type GaAs doped with silicon (Si) is formed on a semi-insulating substrate 1 made of GaAs doped with ) − Platinum (Pt)
- A gate electrode 3 made of sequentially laminated gold (Au),
Source and drain electrodes 4 and 4' are formed by laminating gold/germanium alloy (AuGe) and gold (Au). These gate electrode 3 and source and drain electrodes 4, 4' are all led out onto the semi-insulating substrate 1 from above the active layer 2 to form wiring or lead-out electrodes. Al or Ti in the gate electrode 3 is GaAs
The AuGe in the source and drain electrodes 4, which form a shot contact with the substrate, is an ohmic contact material to the n-type GaAs substrate. Therefore, it was considered that there would be no problem even if both were led out and disposed on the surface of the semi-insulating substrate 1 as described above. However, in reality, in the above structure, a phenomenon of unstable electrical characteristics (substrate bias effect) occurs due to the injection of electrons or holes into the semi-insulating substrate, which adversely affects the electrical characteristics of the semiconductor device. In order to solve this problem, a structure shown in FIG. 2 has already been proposed. In this structure, the source and drain electrodes are divided into contact electrodes 5, 5' and lead wires 6, 6'.
That is, the contact electrodes 5, 5' are formed only on the active layer 2, and the lead wires 6, 6' are selectively formed on the insulating film 7 having openings above the contact electrodes 5, 5'. The contact electrodes 5 and 5' are connected to each other inside. This structure prevents the aforementioned substrate bias effect from occurring, but on the other hand, it is necessary to provide alignment margin for both the contact electrodes 5, 5' and the insulating film 7 when openings are formed therein. Therefore, it is difficult to miniaturize and increase the density of elements. Note that this problem is not limited to source and drain electrodes, but also applies to all electrodes that form ohmic contact, such as resistor electrodes formed on the surface of a semi-insulating substrate.

[Hereinafter, these are collectively referred to as Ohmic electrodes]
occurs in An object of the present invention is to solve the above-mentioned difficulties and provide an improved structure of an FET made of a compound semiconductor that can be miniaturized. This is achieved by leading out onto the insulating film from the inside of the opening and making no contact with the insulating or semi-insulating substrate. An embodiment of the present invention will be described below with reference to a cross-sectional view of the main parts in FIG. As shown in FIG. 3a, a silicon dioxide (SiO ₂ ) film 11 of approximately 4,000 layers is deposited on a semi-insulating substrate 1 made of GaAs by chemical vapor deposition (CVD).

[Å]
This is then selectively removed to form an opening 12, and silicon (Si) is implanted into the opening 12 using an ion implantation method to give a thickness of about 850 mm.

Approximately 15 degrees Celsius

[minutes] After annealing, the dose is approximately 1
×10 ¹²

[cm ^-2 ], average oblique range is approximately 500

An n-type active layer 2 of [Å] is formed. Note that 10 indicates the element substrate formed as described above. Next, the SiO ₂ film 11 is removed once, and then shown in FIG.
Again the thickness is about 6000 as shown

[Å] SiO ₂ film 13
is formed and selectively removed to provide an opening 14 at approximately the same position as the opening 12. Next, a gate electrode 15 made of a mixed metal of TiW and Si is formed in the opening 14 using a sputtering method, a reactive on-etch method, or the like. Note that since the gate electrode 15 made of TiW-Si forms a short contact with GaAs, it may be extended to the outside of the active layer 2, that is, to the surface of the semi-insulating substrate 1, although not shown. Next, using the SiO ₂ film 13 and gate electrode 15 as masks, Si is implanted into the exposed surface of the active layer 2 by ion implantation to form n ⁺ regions 16,1.
6' is formed. The dose of n ⁺ type regions 16, 16' is approximately 1.7×10 ¹³

[cm ^-2 ], average oblique range is approximately 1500

[Å]. The n ⁺ -type regions 16, 16' are source and drain regions, and are formed in self-alignment with the gate electrode 15 according to the manufacturing process described above. Note that the process up to this point is no different from the conventional process. Next, the SiO ₂ film 13 is removed, and as shown in FIG _.

Form to a thickness of [Å]. Next, as shown in FIG. d, the SiO ₂ film 17 is selectively removed to form the source and drain regions 1.
Openings 18, 18' are provided on 6, 16'. Next, by vapor deposition method, ion milling method, etc.
Approximately 200

An AuGe alloy layer with a thickness of [Å] and a layer of approx.
3000

A layer of Au with a thickness of [Å] is selectively deposited, and approximately
450

By applying heat treatment at a temperature of [℃],
making ohmic contact with the source and drain electrodes 16, 16' exposed in the openings 18, 18';
Further, source and drain electrodes 19 and 19' are formed on the SiO ₂ film 17. The semiconductor device according to the present invention obtained as described above is similar to the conventional device.

[See Figure 2] The contact electrodes 5, 5' are removed from the ohmic electrode consisting of the contact electrodes 5, 5' and the lead wires 6, 6' so that the lead wires 6, 6' also serve as contact electrodes. It is something. By adopting such a structure, the semiconductor device of the present invention does not require a positioning margin for forming the contact electrodes 5, 5', and the element can be miniaturized. For example, the gate electrode 15, the openings 18, 18'
The dimensions of each are 2

[μm], or alignment margin is also 2 each

[μm], the width of the active layer is 26 μm in the conventional device.

[μm] In this example, 18

[μm], which is 70

[%] Slightly reduced. Further, according to the present invention, the gate electrode 15 is covered with the insulating film 17, and the extraction electrodes 19 and 19' of the source and drain regions are formed so as to be located on the insulating film 17. The extraction electrodes of the source and drain regions, which are a problem in the self-line process using a mask,
Good insulation from the gate electrode can be obtained, and there is no need to provide alignment margin between the extraction electrodes of the source and drain regions to avoid contact with the gate electrode, making it possible to form fine semiconductor devices with high yield. can. As explained above, according to the present invention, it is possible to miniaturize the pattern of a semiconductor device, and therefore, it is possible to miniaturize and increase the density of a compound semiconductor integrated circuit device.

[Brief explanation of drawings]

1 and 2 are sectional views of essential parts for explaining a conventional semiconductor device, and FIG. 3 is a sectional view of essential parts showing an embodiment of the present invention. In the figure, 1 is an insulating substrate or a semi-insulating substrate, 2 is an active layer, 15 is a gate electrode, 16, 1
6' is a source and drain region, 17 is an insulating film,
18 and 18' are openings, and 19 and 19' are ohmic electrodes.

Claims (1)

[Claims] 1. A step of selectively introducing impurities into the surface of an insulating substrate or a semi-insulating substrate to form an active region, and forming a gate electrode on the active region in direct contact with the active region. and introducing impurities using the gate electrode as a mask to form source and drain regions with higher impurity concentration than the active region on both sides of the substrate surface adjacent to the active region immediately below the gate electrode. forming an insulating film covering the entire surface of the substrate and the gate electrode; and forming an opening in the insulating film over the source and drain regions. defining a first insulating film that covers the side and top surfaces of the gate electrode and a second insulating film that covers the rest of the surface of the substrate; forming source and drain extraction electrodes on the first insulating film, which covers the gate electrode and is a region where this potential is not led out to the surface, and on the second insulating film on the surface of the substrate; A method for manufacturing a semiconductor device, characterized in that: