JPH0353795B2 - - Google Patents
Info
- Publication number
- JPH0353795B2 JPH0353795B2 JP59247123A JP24712384A JPH0353795B2 JP H0353795 B2 JPH0353795 B2 JP H0353795B2 JP 59247123 A JP59247123 A JP 59247123A JP 24712384 A JP24712384 A JP 24712384A JP H0353795 B2 JPH0353795 B2 JP H0353795B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ground
- signal
- polyimide
- entire surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は回路基板、特に、高速コンピユータに
おけるように、高速なスイツチング動作を行なう
集積回路を高密度実装するのに好適な回路基板に
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit board, and particularly to a circuit board suitable for high-density mounting of integrated circuits that perform high-speed switching operations, such as in high-speed computers.
(従来の技術)
従来のこの種の回路基板の一例は、内層にそれ
ぞれが一層または複数の第1のグランド層と第1
の電源層とを有するセラミツク基板の一方の面の
全面ないしはほゞ全面にコンタクトピンを、また
他方の面にはこれらコンタクトピンと電気的に接
続されたパツドをそれぞれ備え、パツド層の上に
ポリイミドを介して少なくとも一つの信号層が形
成されている。(Prior Art) An example of a conventional circuit board of this type includes a first ground layer or a plurality of first ground layers and a first
A ceramic substrate having a power supply layer is provided with contact pins on the entire surface or almost the entire surface of one surface, and pads electrically connected to these contact pins are provided on the other surface, and polyimide is formed on the pad layer. At least one signal layer is formed therebetween.
(発明が解決しようとする問題点)
このような従来構成においては、信号層はグラ
ンド層または電源層との間隔が大きいために、信
号線の特性インピーダンスが高く、信号線間のク
ロストーク雑音が大きいという問題点がある。(Problems to be Solved by the Invention) In such a conventional configuration, the distance between the signal layer and the ground layer or power layer is large, so the characteristic impedance of the signal line is high and crosstalk noise between the signal lines is high. The problem is that it is large.
したがつて、本発明の目的は、信号線間のクロ
ストーク雑音の低下を図つた回路基板を提供する
ことにある。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a circuit board that reduces crosstalk noise between signal lines.
(問題点を解決するための手段)
そのために、第1の本発明の回路基板は、内層
にそれぞれが一つまたは複数の第1のグランド層
と第1の電源層とを有するセラミツク基板の一方
の面の全面ないしはほゞ全面にコンタクトピン
を、また他方の面には該コンタクトピンの電気的
に接続されたパツドをそれぞれ備え、該パツドの
上にポリイミドを介して少なくとも一つの信号層
を、該信号層の最上層の上に前記ポリイミドを介
して第3のグランドまたは電源層をそれぞれ形成
したことを特徴とする。(Means for Solving the Problems) To this end, the circuit board of the first aspect of the present invention is made of one of the ceramic substrates each having one or more first ground layers and a first power layer in the inner layer. A contact pin is provided on the entire surface or substantially the entire surface of the contact pin, and a pad to which the contact pin is electrically connected is provided on the other surface, and at least one signal layer is provided on the pad via polyimide, A third ground or power supply layer is formed on the uppermost layer of the signal layer via the polyimide.
また、第2の本発明の回路基板は、内層にそれ
ぞれが一つまたは複数の第1のグランド層と第1
の電源層とを有するセラミツク基板の一方の面の
全面ないしはほゞ全面にコンタクトピンを、また
他方の面には該コンタクトピンと電気的に接続さ
れたパツドをそれぞれ備え、該パツドと同一層に
メツシユ状の第2のグランドまたは電源層を、該
層の上にポリイミドを介して少なくとも一つの信
号層を、該信号層の最上層の上に前記ポリイミド
を介して第3のグランドまたは電源層をそれぞれ
形成したことを特徴とする。 Further, the circuit board of the second aspect of the present invention has one or more first ground layers and a first
A ceramic substrate having a power supply layer is provided with a contact pin on the entire surface or almost the entire surface of one surface, and a pad electrically connected to the contact pin is provided on the other surface, and a mesh is provided on the same layer as the pad. a second ground or power layer on top of the layer, at least one signal layer via polyimide, and a third ground or power layer on the top layer of the signal layer via the polyimide, respectively. It is characterized by the fact that it has been formed.
(実施例)
第2の本発明の一実施例の断面図を示す第1図
を参照すると、本実施例は、内層に第1のグラン
ド層G1と第1の電源層P1とを有するセラミツ
ク基板CBの下面全面にコンタクトピンCPを、ま
た上面全面にコンタクトピンCPとはスルーホー
ルTHを介して電気的に接続されたパツドPDを
それぞれ備え、パツドPDと同一層にメツシユ状
の第2の電源層P2を、この第2の電源層P2の
上にポリイミドPIを絶縁層とする第1の信号層
S1と第2の信号層S2を、第2の信号層S2の
上にポリイミドPIを介して第2のグランド層G
2がそれぞれ形成されている。ポリイミドPIは
高絶縁性と低比誘電率とを有する良質の絶縁体で
あり、この種の回路基板によく採用される。(Example) Referring to FIG. 1 showing a sectional view of an example of the second invention, this example is a ceramic substrate having a first ground layer G1 and a first power layer P1 in the inner layer. A contact pin CP is provided on the entire bottom surface of the CB, and a pad PD is electrically connected to the contact pin CP via a through hole TH on the entire top surface, and a mesh-shaped second power supply is provided on the same layer as the pad PD. A first signal layer S1 and a second signal layer S2 each having a polyimide PI as an insulating layer are formed on the second power supply layer P2, and a first signal layer S1 and a second signal layer S2 are formed on the second signal layer S2 via the polyimide PI. Second ground layer G
2 are formed respectively. Polyimide PI is a high-quality insulator with high insulation properties and low dielectric constant, and is often used in this type of circuit board.
図示を省略するが、集積回路チツプが第2のグ
ランド層G2の上に実装され、第1の信号層S
1、第2の信号層S2、第1の電源層P1、第2
の電源層P2、第1のグランド層G1および第2
のグランド層G2とスルーホールを介して接続さ
れる。 Although not shown, an integrated circuit chip is mounted on the second ground layer G2, and the first signal layer S
1, second signal layer S2, first power supply layer P1, second
power supply layer P2, first ground layer G1 and second
It is connected to the ground layer G2 through a through hole.
第1図から明らかなように、セラミツク基板
CBとポリイミドPIの間には第2の電源層P2が
介在するために、両者は電磁的に遮へいされる。
したがつて、第1の信号層S1および第2の信号
層S2における実効比誘電率εreは、ポリイミド
の比誘電率にほゞ等しくなる。第1の信号層S1
および第2の信号層S2における信号の伝搬遅延
時間T(ns/m)は、一般に、次式で表わされる
ために、
T=3.335√re
伝搬遅延時間Tは、実効誘電率εreの低下につ
れて小さくなることがわかる。 As is clear from Figure 1, the ceramic substrate
Since the second power supply layer P2 is interposed between CB and polyimide PI, both are electromagnetically shielded.
Therefore, the effective relative permittivity ε re of the first signal layer S1 and the second signal layer S2 is approximately equal to the relative permittivity of polyimide. First signal layer S1
The propagation delay time T (ns/m) of the signal in the second signal layer S2 is generally expressed by the following equation, so T=3.335√ re The propagation delay time T increases as the effective permittivity ε re decreases. You can see that it becomes smaller.
また、第1の信号層S1および第2の信号層S
2は、その上下が第2のグランド層G2と第2の
電源層P2とで覆われるために、第1の信号層S
1および第2の信号層S2とグランド層または電
源層との間隔が小さくなり、特性インピーダンス
は低下し、信号線間のクロストーク雑音が低下す
る。 Further, the first signal layer S1 and the second signal layer S
2 is covered with the second ground layer G2 and the second power supply layer P2 on its upper and lower sides, so that the first signal layer S
The distance between the first and second signal layers S2 and the ground layer or power supply layer is reduced, the characteristic impedance is reduced, and crosstalk noise between signal lines is reduced.
第1の本発明の一実施例は、第1図において、
第2の電源層P2を除去した図によつて容易に示
すことができる。 An embodiment of the first invention is shown in FIG.
This can be easily illustrated by a diagram in which the second power supply layer P2 is removed.
この場合にも、第2のグランド層G2の存在の
ために、第1の信号層S1および第2の信号層S
2とグランド層との間隔が小さくなり、特性イン
ピーダンスは低下し、信号線間のクロストーク雑
音が低下する。 Also in this case, due to the presence of the second ground layer G2, the first signal layer S1 and the second signal layer S
2 and the ground layer becomes smaller, the characteristic impedance decreases, and crosstalk noise between signal lines decreases.
しかしながら、セラミツク基板CBとポリイミ
ドPIとを電磁的に遮へいするものが無いために、
第1の信号層S1および第2の信号層S2におけ
る信号の伝搬遅延時間は、従来とほとんど同程度
のまゝである。 However, since there is nothing to electromagnetically shield the ceramic substrate CB and polyimide PI,
The signal propagation delay times in the first signal layer S1 and the second signal layer S2 remain almost the same as in the conventional case.
以上に述べたすべての実施例においては、第1
の電源層P1および第1のグランド層G1は、そ
れぞれ一層であるが、これらは複数層であつても
よい。 In all the embodiments described above, the first
The power supply layer P1 and the first ground layer G1 each have a single layer, but they may have multiple layers.
また、第2の電源層P2と第2のグランド層G
2とが入れ替つてもよいし、両方の層とも電源層
あるいはグランド層であつてもよい。 In addition, the second power layer P2 and the second ground layer G
2 may be exchanged with each other, and both layers may be a power supply layer or a ground layer.
(発明の効果)
本発明によれば、以上のような構成の採用によ
つて、信号線間のクロストーク雑音を低下させ、
高速スイツチング動作を行なう集積回路を高密度
に実装するのに好適な回路基板を得ることができ
るようになる。(Effects of the Invention) According to the present invention, by employing the above configuration, crosstalk noise between signal lines is reduced,
It becomes possible to obtain a circuit board suitable for mounting integrated circuits that perform high-speed switching operations at high density.
第1図は第2の本発明の一実施例を示す。
CB……セラミツク基板、PI……ポリイミド、
CP……コンタクトピン、PD……パツド、P1…
…第1の電源層、P2……第2の電源層、G1…
…第1のグランド層、G2……第2のグランド
層、S1……第1の信号層、S2……第2の信号
層。
FIG. 1 shows an embodiment of the second invention. CB...ceramic substrate, PI...polyimide,
CP...Contact pin, PD...Packed, P1...
...First power layer, P2... Second power layer, G1...
...first ground layer, G2...second ground layer, S1...first signal layer, S2...second signal layer.
Claims (1)
ランド層と第1の電源層とを有するセラミツク基
板の一方の面の全面ないしはほゞ全面にコンタク
トピンを、また他方の面には該コンタクトピンと
電気的に接続されたパツドをそれぞれ備え、該パ
ツドの上にポリイミドを介して少なくとも一つの
信号層を、該信号層の最上層の上に前記ポリイミ
ドを介して第3のグランドまたは電源層をそれぞ
れ形成したことを特徴とする回路基板。 2 内層にそれぞれが一つまたは複数の第1のグ
ランド層と第1の電源層とを有するセラミツク基
板の一方の面の全面ないしはほゞ全面にコンタク
トピンを、また他方の面には該コンタクトピンと
電気的に接続されたパツドをそれぞれ備び、該パ
ツドと同一層にメツシユ状の第2のグランドまた
は電源層を、該層の上にポリイミドを介して少な
くとも一つの信号層を、該信号層の最上層の上に
前記ポリイミドを介して第3のグランドまたは電
源層をそれぞれ形成したことを特徴とする回路基
板。[Claims] 1. A ceramic substrate having one or more first ground layers and a first power supply layer in its inner layers, contact pins on the entire surface or almost the entire surface of one surface, and contact pins on the entire surface or substantially the entire surface of one surface, and Each surface is provided with a pad electrically connected to the contact pin, at least one signal layer is formed on the pad through polyimide, and a third signal layer is formed on the top layer of the signal layer through polyimide. A circuit board characterized by forming a ground layer or a power layer. 2 A ceramic substrate each having one or more first ground layers and a first power supply layer in its inner layer has contact pins on the entire surface or almost the entire surface of one surface, and the contact pins and the other surface on the other surface. A mesh-shaped second ground or power layer is provided on the same layer as the pad, at least one signal layer is provided on the layer through polyimide, and a second ground or power layer is provided on the same layer as the pad. A circuit board characterized in that a third ground or power layer is formed on the uppermost layer via the polyimide.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59247123A JPS61125196A (en) | 1984-11-22 | 1984-11-22 | Circuit board |
| US06/724,587 US4754371A (en) | 1984-04-27 | 1985-04-18 | Large scale integrated circuit package |
| FR8506423A FR2563656B1 (en) | 1984-04-27 | 1985-04-26 | LARGE-SCALE INTEGRATION CIRCUIT BLOCK |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59247123A JPS61125196A (en) | 1984-11-22 | 1984-11-22 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61125196A JPS61125196A (en) | 1986-06-12 |
| JPH0353795B2 true JPH0353795B2 (en) | 1991-08-16 |
Family
ID=17158771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59247123A Granted JPS61125196A (en) | 1984-04-27 | 1984-11-22 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125196A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4880684A (en) * | 1988-03-11 | 1989-11-14 | International Business Machines Corporation | Sealing and stress relief layers and use thereof |
| JP2645233B2 (en) * | 1995-04-21 | 1997-08-25 | テインチイチイイエ ヨウシェンコンス | Low crosstalk signal transmission medium |
-
1984
- 1984-11-22 JP JP59247123A patent/JPS61125196A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61125196A (en) | 1986-06-12 |
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