JPH0353824B2 - - Google Patents
Info
- Publication number
- JPH0353824B2 JPH0353824B2 JP10556085A JP10556085A JPH0353824B2 JP H0353824 B2 JPH0353824 B2 JP H0353824B2 JP 10556085 A JP10556085 A JP 10556085A JP 10556085 A JP10556085 A JP 10556085A JP H0353824 B2 JPH0353824 B2 JP H0353824B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- frequency
- modulated signal
- signal
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 39
- 238000007599 discharging Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/12—Modulator circuits; Transmitter circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はFSK(Frequency Sift Keying)方式
の変調回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulation circuit using FSK (Frequency Shift Keying).
FSK方式の変調回路としては、従来より種々
のものが提案されている。
Various types of FSK modulation circuits have been proposed in the past.
第3図は従来使用されている所謂デイジタル方
式の変調回路の一例を示すブロツク線図であり、
31は被変調信号の入力端子、32は切換回路、
35は所定周波数のクロツク信号を出力する発振
器、36,37は前置分周器、38は主分周器、
39はローパスフイルタ、40は変調信号(正弦
波)の出力端子である。 FIG. 3 is a block diagram showing an example of a conventionally used so-called digital modulation circuit.
31 is an input terminal for a modulated signal; 32 is a switching circuit;
35 is an oscillator that outputs a clock signal of a predetermined frequency; 36 and 37 are pre-frequency dividers; 38 is a main frequency divider;
39 is a low-pass filter, and 40 is an output terminal for a modulation signal (sine wave).
前置分周器36は発振器35からのクロツク信
号を第1の分周比N1で分周し、前置分周器37
は発振器35からのクロツク信号を第2の分周比
N2で分周する。また、切換回路32は入力端子
31を介して加えられる被変調信号が“H”の時
はスイツチ33の接点をA側にし、被変調信号が
“L”の場合はスイツチ33の接点をB側にする。
従つて、被変調信号が“H”の場合には前置分周
器36の出力信号(矩形波)が主分周器38に加
えられ、被変調信号が“L”の場合には前置分周
器37の出力信号(矩形波)が主分周器38に加
えられることになる。主分周器38は前置分周器
36或いは前置分周器37からの信号を所定の分
周比Nで分周してローパスフイルタ39に加え、
これによりローパスフイルタ39から被変調信号
の“H”、“L”に対応した周波数の正弦波が出力
される。 The prescaler 36 divides the clock signal from the oscillator 35 by a first frequency division ratio N1 , and then divides the clock signal from the oscillator 35 by a first frequency division ratio N1.
is the clock signal from the oscillator 35 by the second frequency division ratio.
Divide by N2 . Further, the switching circuit 32 sets the contact of the switch 33 to the A side when the modulated signal applied via the input terminal 31 is "H", and sets the contact of the switch 33 to the B side when the modulated signal is "L". Make it.
Therefore, when the modulated signal is "H", the output signal (rectangular wave) of the prescaler 36 is applied to the main frequency divider 38, and when the modulated signal is "L", the output signal (rectangular wave) of the prescaler The output signal (rectangular wave) of the frequency divider 37 will be applied to the main frequency divider 38. The main frequency divider 38 divides the signal from the pre-frequency divider 36 or 37 by a predetermined frequency division ratio N and applies it to the low-pass filter 39.
As a result, a sine wave having a frequency corresponding to "H" and "L" of the modulated signal is output from the low-pass filter 39.
しかし上述した従来例は主分周器38の出力信
号(矩形波)をローパスフイルタ39に加えるこ
とにより、変調信号(正弦波)を得るようにして
いるため、次のような問題点がある。即ち、主分
周器38の出力信号には、約−9.5dBmの3倍調
波成分及び約−14.0dBmの5倍調波成分が含まれ
ているものであるから〔但し、主分周器38の出
力信号に含まれる基本波成分(正弦波成分)のレ
ベルを0dBmとする〕、不要送出レベルの基準を
満足させるためには、高域阻止特性の良い高価な
ローパスフイルタを使用する必要があり、従つて
装置が高価になる問題があつた。 However, in the conventional example described above, the modulation signal (sine wave) is obtained by applying the output signal (rectangular wave) of the main frequency divider 38 to the low-pass filter 39, and therefore there are the following problems. That is, the output signal of the main frequency divider 38 contains a third harmonic component of approximately -9.5 dBm and a fifth harmonic component of approximately -14.0 dBm. The level of the fundamental wave component (sine wave component) included in the output signal of 38 is set to 0 dBm], and in order to satisfy the criteria for unnecessary transmission level, it is necessary to use an expensive low-pass filter with good high-frequency rejection characteristics. Therefore, there was a problem that the equipment became expensive.
また、第4図はアナログ方式と呼ばれている他
の従来例のブロツク線図であり、41は被変調信
号の入力端子、42,48は切換回路、43〜4
6はスイツチ、47は比較器、49はローパスフ
イルタ、50は出力端子、51はコンデンサ、5
2〜55は抵抗である。尚、抵抗52,53の抵
抗値はそれぞれ異なるものであり、また抵抗5
4,55の抵抗値もそれぞれ異なるものである。 FIG. 4 is a block diagram of another conventional example called an analog system, in which 41 is an input terminal for a modulated signal, 42 and 48 are switching circuits, and 43 to 4
6 is a switch, 47 is a comparator, 49 is a low-pass filter, 50 is an output terminal, 51 is a capacitor, 5
2 to 55 are resistances. Note that the resistance values of the resistors 52 and 53 are different from each other, and the resistance values of the resistors 52 and 53 are different from each other.
The resistance values of 4 and 55 are also different.
切換回路42は入力端子41を介して加えらえ
る被変調信号が“H”の場合はスイツチ43,4
4の接点を共にA側にし、被変調信号が“L”の
場合はスイツチ43,44の接点を共にB側にす
る。比較器47はコンデンサ51の両端に現れる
電圧Vcと第1、第2の閾値がV1、V2(V1>V2)
とを比較し、電圧Vcが第1の閾値V1以上となつ
てから第2の閾値V2以下になるまでの間はその
出力信号を“L”に保持し、電圧Vcが第2の閾
値V2以下になつてから第1の閾値V1以上になる
までの間はその出力信号を“H”に保持する。ま
た、切換回路48は比較器47の出力信号が
“H”の場合はスイツチ45をオン状態、スイツ
チ46をオフ状態にし、比較器47の出力信号が
“L”の場合はスイツチ45をオフ状態、スイツ
チ46をオン状態にする。 The switching circuit 42 switches switches 43 and 4 when the modulated signal applied via the input terminal 41 is "H".
Both the contacts of switches 43 and 44 are set to the A side, and when the modulated signal is "L", the contacts of switches 43 and 44 are both set to the B side. The comparator 47 has the voltage V c appearing across the capacitor 51 and the first and second thresholds V 1 and V 2 (V 1 >V 2 ).
The output signal is held at "L" from when the voltage V c becomes above the first threshold V 1 until it becomes below the second threshold V 2 , and when the voltage V c becomes the second The output signal is held at "H" from when it becomes equal to or less than the first threshold value V2 until it becomes equal to or more than the first threshold value V1 . Further, when the output signal of the comparator 47 is "H", the switching circuit 48 turns the switch 45 on and the switch 46 off, and when the output signal of the comparator 47 is "L", the switch 45 is turned off. , turns on the switch 46.
従つて、入力端子41からの被変調信号が
“H”の場合は、抵抗52、スイツチ43,45
を介して流れる充電電流によりコンデンサ51が
充電され、その両端に現れる電圧Vcが第1の閾
値V1以上となるとコンデンサ51の充電電荷は
スイツチ46,44、抵抗54を介して放電され
る。そして、コンデンサ51の両端に現れる電圧
Vcが第2の閾値V2以下となると再び抵抗52、
スイツチ43,45を介して流れる充電電流によ
りコンデンサ51が充電され、その両端に現れる
電圧Vcは次第に増加する。以上の動作が繰返し
行なわれることにより、コンデンサ51の両端に
は抵抗52,54、コンデンサ51の時定数に応
じた三角波が現れることになる。 Therefore, when the modulated signal from the input terminal 41 is "H", the resistor 52, switches 43, 45
The capacitor 51 is charged by the charging current flowing through the capacitor 51, and when the voltage Vc appearing across the capacitor becomes equal to or higher than the first threshold value V1, the charge in the capacitor 51 is discharged via the switches 46, 44 and the resistor 54. Then, the voltage appearing across the capacitor 51 is
When V c becomes less than the second threshold V 2 , the resistor 52
Capacitor 51 is charged by the charging current flowing through switches 43 and 45, and the voltage V c appearing across it gradually increases. By repeating the above operation, a triangular wave corresponding to the time constant of the resistors 52, 54 and the capacitor 51 appears at both ends of the capacitor 51.
また、入力端子41からの被変調信号が“L”
の場合は、抵抗53、スイツチ43,45を介し
て流れる充電電流によりコンデンサ51が充電さ
れ、その両端に現れる電圧Vcが第1の閾値V1以
上となるとコンデンサ51の充電電荷はスイツチ
46,44、抵抗55を介して放電される。そし
て、コンデンサ51の両端に現れる電圧Vcが第
2の閾値V2以下となると再び抵抗53、スイツ
チ43,45を介して流れる充電電流によりコン
デンサ51が充電され、その両端に現れる電圧
Vcは次第に増加する。以上の動作が繰返し行な
われることにより、コンデンサ51の両端には抵
抗53,55、コンデンサ51の時定数に応じた
三角波が現れることになる。 Also, the modulated signal from the input terminal 41 is “L”
In this case, the capacitor 51 is charged by the charging current flowing through the resistor 53 and the switches 43 and 45, and when the voltage V c appearing across the capacitor becomes equal to or higher than the first threshold value V 1 , the charge in the capacitor 51 is transferred to the switch 46, 44, and is discharged through the resistor 55. When the voltage V c appearing across the capacitor 51 becomes less than the second threshold value V 2 , the capacitor 51 is charged again by the charging current flowing through the resistor 53 and the switches 43 and 45, and the voltage appearing across the capacitor 51 is charged again.
V c gradually increases. By repeating the above operations, a triangular wave corresponding to the time constant of the resistors 53, 55 and the capacitor 51 appears at both ends of the capacitor 51.
そして、上述したようにして得られた三角波を
ローパスフイルタ49を通すことにより、被変調
信号の“H”、“L”に対応した周波数の変調信号
(正弦波)が出力端子40に得られる。 Then, by passing the triangular wave obtained as described above through the low-pass filter 49, a modulated signal (sine wave) having a frequency corresponding to "H" and "L" of the modulated signal is obtained at the output terminal 40.
上述した実施例に於いては、三角波の基本波成
分のレベルを0dBmとすると、三角波に含まれる
3倍調波成分及び5倍調波成分はそれぞれ約−
19.0dBm、−28.0dBmとなり、第3図に示したデ
イジタル方式の実施例で用いたローパスフイルタ
39よりも安価なローパスフイルタを使用しても
不要送出レベルの基準を満足させることができる
が次のような問題があつた。即ち、上述した実施
例に於いては、被変調信号の“H”、“L”に対応
した変調信号の周波数が抵抗52〜55、コンデ
ンサ51の時定数により決定されるものであるか
ら、温度変化、経年変化等により変調波の周波数
が変動する問題があつた。 In the above embodiment, if the level of the fundamental wave component of the triangular wave is 0 dBm, the third harmonic component and the fifth harmonic component contained in the triangular wave are approximately -
19.0 dBm and -28.0 dBm, which is cheaper than the low-pass filter 39 used in the digital embodiment shown in Fig. 3, and can still satisfy the unnecessary transmission level criteria. I had a problem like this. That is, in the above embodiment, since the frequency of the modulated signal corresponding to "H" and "L" of the modulated signal is determined by the time constants of the resistors 52 to 55 and the capacitor 51, the temperature There was a problem that the frequency of the modulated wave fluctuated due to change, aging, etc.
本発明は前述の如き問題点を解決したものであ
り、その目的は経済的な構成で、且つ温度変化等
に対しても安定な変調回路を提供することにあ
る。
The present invention solves the above-mentioned problems, and its purpose is to provide a modulation circuit that is economical in structure and stable against temperature changes and the like.
本発明は前述の如き問題点を解決するため、所
定周波数のクロツク信号を出力する発振器と、該
発振器からのクロツク信号をそれぞれ第1、第2
の分周比で分周する第1、第2の分周器と、被変
調信号の状態に応じて前記第1、第2の分周器の
出力信号の内の何れか一方を出力する切換手段
と、第1、第2の充電電流を出力する第1、第2
の充電回路と、第1、第2の放電電流が流れる第
1、第2の放電回路と、前記切換手段の出力信号
と前記被変調信号の状態とに基づいて、コンデン
サに前記第1、第2の充電回路或いは前記第1、
第2の放電回路の内の何れか1つを接続し、前記
コンデンサの両端に梯形波電圧を生じさせる制御
手段と、前記コンデンサの両端に現れる梯形波電
圧から基本波成分を取出すローパスフイルタとを
設けたものである。
In order to solve the above-mentioned problems, the present invention includes an oscillator that outputs a clock signal of a predetermined frequency, and a clock signal from the oscillator that is connected to a first clock and a second clock, respectively.
first and second frequency dividers that divide the frequency at a frequency division ratio, and switching that outputs one of the output signals of the first and second frequency dividers depending on the state of the modulated signal. first and second means for outputting first and second charging currents;
a charging circuit, first and second discharge circuits through which first and second discharge currents flow, and a state of the first and second discharge currents in the capacitor based on the output signal of the switching means and the state of the modulated signal. 2 charging circuit or the first charging circuit;
a control means for connecting one of the second discharge circuits to generate a trapezoidal voltage across the capacitor; and a low-pass filter for extracting a fundamental wave component from the trapezoidal voltage appearing across the capacitor. It was established.
コンデンサの両端に現れる梯形波より基本波成
分を取出すものであるから、ローパスフイルタを
高域阻止特性の低いものとすることができる。ま
た、コンデンサの両端に現れる梯形波の周波数は
クロツク信号の周波数により定まるものであるか
ら、温度変化、平年変化等に対して装置を安定な
ものとすることができる。
Since the fundamental wave component is extracted from the trapezoidal wave appearing at both ends of the capacitor, the low-pass filter can have low high-frequency rejection characteristics. Furthermore, since the frequency of the trapezoidal wave appearing at both ends of the capacitor is determined by the frequency of the clock signal, the device can be made stable against temperature changes, normal changes, etc.
第1図は本発明の実施例のブロツク線図であ
り、1は被変調信号の入力端子、2,7は切換回
路、3は所定周波数のクロツク信号を出力する水
晶発振器等の発振器、4,5は前置分周器、6は
主分周器、8,9は定電流回路等からなる充電回
路、10,11は定電流回路等からなる放電回
路、12はコンデンサ、13はローパスフイル
タ、14は変調信号の出力端子、15〜19はス
イツチである。
FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an input terminal for a modulated signal, 2 and 7 are switching circuits, 3 is an oscillator such as a crystal oscillator that outputs a clock signal of a predetermined frequency, 4, 5 is a pre-frequency divider, 6 is a main frequency divider, 8 and 9 are charging circuits consisting of constant current circuits, etc., 10 and 11 are discharging circuits consisting of constant current circuits, etc., 12 is a capacitor, 13 is a low-pass filter, 14 is an output terminal for a modulation signal, and 15 to 19 are switches.
また、第2図は第1図の動作説明図であり、以
下同図を参照して第1図の動作を説明する。 Further, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and the operation of FIG. 1 will be explained below with reference to the same figure.
前置分周器4は発振器3からのクロツク信号を
第1の分周比N1で分周し、前置分周器5は発振
器3からのクロツク信号を第2の分周比N2で分
周するものであり、切換回路2は入力端子1を介
して加えられる被変調信号が“H”の時はスイツ
チ15,16,19の接点をA側にし、被変調信
号が“L”の場合はスイツチ15,16,19の
接点をB側にするものである。また、主分周器6
はスイツチ15を介して加えられる前置分周器4
或いは前置分周器5の出力信号を所定の分周比N
で分周して切換回路7に加えるものである。従つ
て、入力端子1に第2図Aに示す被変調信号が加
えられたとすると、主分周器6の出力信号は同図
Bに示すものとなる。 Prescaler 4 divides the clock signal from oscillator 3 by a first division ratio N1 , and prescaler 5 divides the clock signal from oscillator 3 by a second division ratio N2 . The switching circuit 2 sets the contacts of switches 15, 16, and 19 to the A side when the modulated signal applied via the input terminal 1 is "H", and when the modulated signal is "L" In this case, the contacts of switches 15, 16, and 19 are set to the B side. In addition, the main frequency divider 6
prescaler 4 added via switch 15
Alternatively, the output signal of the prescaler 5 is divided by a predetermined frequency division ratio N.
The frequency is divided by and applied to the switching circuit 7. Therefore, if the modulated signal shown in FIG. 2A is applied to the input terminal 1, the output signal of the main frequency divider 6 will be as shown in FIG. 2B.
また、切換回路7は主分周器6の出力信号が
“H”の場合はスイツチ17,18をそれぞれオ
ン、オフ状態にし、主分周器6の出力信号が
“L”の場合はスイツチ17,18をそれぞれオ
フ、オン状態にするものであり、従つて主分周器
6より第2図Bに示す信号が加えられたとする
と、スイツチ17,18の状態はそれぞれ同図
C,Dに示すものとなる。 Further, when the output signal of the main frequency divider 6 is "H", the switching circuit 7 turns on and off the switches 17 and 18, respectively, and when the output signal of the main frequency divider 6 is "L", the switch 17 and 18 are turned on and off, respectively. , 18 are turned off and on, respectively. Therefore, if the signal shown in FIG. 2B is applied from the main frequency divider 6, the states of switches 17 and 18 are shown in FIG. 2C and D, respectively. Become something.
また、充電回路8,9はそれぞれ第1、第2の
充電電流Ic1、Ic2をコンデンサ12に供給するも
のであり、放電回路10,11はそれぞれ第1、
第2の放電電流Id1、Id2を流すものである。尚、
本実施例に於いてはψがπ/3となるように、コ
ンデンサ12の容量及び放電、充電電流Ic1、
Ic2、Id1、Id2が定められているものとする。従
つて、入力端子1に第2図Aに示す被変調信号が
加えられたとすると、コンデンサ12の両端に
は、同図Eに示すような、被変調信号の“H”、
“L”に対応した周波数を有する梯形波電圧Vcが
現れる。そして、これをローパスフイルタ13を
通すことにより、同図Fに示すような被変調信号
の“H”、“L”に対応した周波数を有する変調信
号(正弦波)が得られる。 Further, the charging circuits 8 and 9 supply the first and second charging currents Ic1 and Ic2 to the capacitor 12, respectively, and the discharging circuits 10 and 11 supply the first and second charging currents Ic1 and Ic2, respectively, to the capacitor 12.
This is to flow second discharge currents Id1 and Id2. still,
In this embodiment, the capacitance and discharge of the capacitor 12, the charging current Ic1,
It is assumed that Ic2, Id1, and Id2 are defined. Therefore, if the modulated signal shown in FIG. 2A is applied to the input terminal 1, the "H" of the modulated signal as shown in FIG.
A trapezoidal voltage V c having a frequency corresponding to "L" appears. Then, by passing this through the low-pass filter 13, a modulated signal (sine wave) having a frequency corresponding to "H" and "L" of the modulated signal as shown in FIG. F is obtained.
ここで、コンデンサ12の両端に現れる電圧
Vcをフーリエ展開すると、
Vc=V/ψπ{sin(2n+1)・/(2n+1)2
・sin(2n+1)ωt}
(n=0、1、2、……)
となる。また、前述したように、本実施例ではψ
=π/3となるように、コンデンサ12の容量及
び放電、充電電流Ic1、Ic2、Id2、Id2を設定して
いるものであるから、Vcの基本波成分を0dBmと
して、その3倍、5倍調波成分を求めると、3倍
調波成分は全く存在せず、5倍調波成分は約−
28.0dBmとなる。これから判るように、本実施例
によれば第3図、第4図に示した従来例に比較し
て3倍、5倍調波成分を少ないものとすることが
できるものであるから、高域阻止特性の低い簡便
なローパスフイルタを使用しても、不要送出レベ
ルの基準を満足させることができ、従つて本実施
例によれば装置を経済的に構成することができ
る。また、更に、コンデンサ12の両端に現れる
梯形波電圧の周波数は水晶発振器等の発振器3か
ら出力されるクロツク信号によつて定められるも
のであるから、第4図に示した従来例に比較して
温度変化、経年変化等に対して装置を安定なもの
とすることができる。 Here, the voltage appearing across the capacitor 12 is
When V c is expanded by Fourier, V c =V/ψπ{sin(2n+1)・/(2n+1) 2・sin(2n+1)ωt} (n=0, 1, 2,...). In addition, as mentioned above, in this example, ψ
Since the capacitance and discharging and charging currents Ic1, Ic2, Id2, and Id2 of the capacitor 12 are set so that = π/3, assuming that the fundamental wave component of V c is 0 dBm, 3 times that, 5 When calculating the harmonic components, there is no third harmonic component at all, and the fifth harmonic component is approximately -
It becomes 28.0dBm. As can be seen, according to this embodiment, the 3rd and 5th harmonic components can be reduced compared to the conventional example shown in FIGS. 3 and 4, so that the high frequency Even if a simple low-pass filter with low blocking characteristics is used, it is possible to satisfy the criterion for the unnecessary emission level, and therefore, according to this embodiment, the apparatus can be constructed economically. Furthermore, since the frequency of the trapezoidal voltage appearing across the capacitor 12 is determined by the clock signal output from the oscillator 3, such as a crystal oscillator, it is different from the conventional example shown in FIG. The device can be made stable against temperature changes, secular changes, and the like.
以上説明したように、本発明は、所定周波数の
クロツク信号を出力する水晶発振器等からなる発
振器と、該発振器からのクロツク信号をそれぞれ
第1、第2の分周比で分周する第1、第2の分周
器と、被変調信号の状態に応じて前記第1、第2
の分周器の出力信号の内の何れか一方を出力する
切換回路2、スイツチ15等からなる切換手段
と、第1、第2の充電電流を出力する第1、第2
の充電回路と、第1、第2の放電電流が流れる第
1、第2の放電回路と、前記切換手段の出力信号
と前記被変調信号の状態とに基づいて、コンデン
サに前記第1、第2の充電回路或いは前記第1、
第2の放電回路の内の何れか1つを接続し、前記
コンデンサの両端に梯形波電圧を生じるさせる切
換回路2,7、主分周器6等からなる制御手段
と、前記コンデンサの両端に現れる梯形波電圧か
ら基本波成分を取出すローパスフイルタとを設け
たものであり、コンデンサの両端に現れる梯形波
より基本波成分を取出すものであるから、高域阻
止特性の低い安価なローパスフイルタを使用する
ことができ、従つて装置を経済的に構成すること
ができる利点がある。また、コンデンサの両端に
現れる梯形波の周波数はクロツク信号の周波数に
より決るものであるから、温度変化、平年変化等
に対して装置を安定なものとすることができる利
点もある。
As explained above, the present invention includes an oscillator such as a crystal oscillator that outputs a clock signal of a predetermined frequency, and a first clock that divides the clock signal from the oscillator by first and second frequency division ratios, respectively. a second frequency divider, and the first and second frequency dividers depending on the state of the modulated signal.
a switching means comprising a switching circuit 2, a switch 15, etc., which outputs one of the output signals of the frequency divider; and first and second charging currents which output the first and second charging currents.
a charging circuit, first and second discharge circuits through which first and second discharge currents flow, and a state of the first and second discharge currents in the capacitor based on the output signal of the switching means and the state of the modulated signal. 2 charging circuit or the first charging circuit;
A control means comprising a switching circuit 2, 7, a main frequency divider 6, etc. connected to one of the second discharge circuits to generate a trapezoidal voltage across the capacitor; It is equipped with a low-pass filter that extracts the fundamental wave component from the trapezoidal wave voltage that appears.Since the fundamental wave component is extracted from the trapezoidal wave that appears at both ends of the capacitor, an inexpensive low-pass filter with low high-frequency rejection characteristics is used. This has the advantage that the device can be constructed economically. Further, since the frequency of the trapezoidal wave appearing at both ends of the capacitor is determined by the frequency of the clock signal, there is an advantage that the device can be made stable against temperature changes, normal changes, etc.
第1図は本発明の実施例のブロツク線図、第2
図は第1図の動作説明図、第3図、第4図はそれ
ぞれ異なる従来例のブロツク線図である。
1は入力端子、2,7は切換回路、3は発振
器、4,5は前置分周器、6は主分周器、8,9
は充電回路、10,11は放電回路、12はコン
デンサ、13はローパスフイルタ、14は出力端
子、15〜19はスイツチである。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation of FIG. 1, and FIGS. 3 and 4 are block diagrams of different conventional examples. 1 is an input terminal, 2 and 7 are switching circuits, 3 is an oscillator, 4 and 5 are pre-frequency dividers, 6 is a main frequency divider, 8 and 9
1 is a charging circuit, 10 and 11 are discharge circuits, 12 is a capacitor, 13 is a low-pass filter, 14 is an output terminal, and 15 to 19 are switches.
Claims (1)
と、 該発振器からのクロツク信号をそれぞれ第1、
第2の分周比で分周する第1、第2の分周器と、 被変調信号の状態に応じて前記第1、第2の分
周器の出力信号の内の何れか一方を出力する切換
手段と、 第1、第2の充電電流を出力する第1、第2の
充電回路と、 第1、第2の放電電流が流れる第1、第2の放
電回路と、 前記切換手段の出力信号と前記被変調信号の状
態とに基づいて、コンデンサに前記第1、第2の
充電回路或いは前記第1、第2の放電回路の内の
何れか1つを接続し、前記コンデンサの両端に梯
形波電圧を生じさせる制御手段と、 前記コンデンサの両端に現れる梯形波電圧から
基本波成分を取出すローパスフイルタとを備えた
ことを特徴とする変調回路。[Claims] 1. An oscillator that outputs a clock signal of a predetermined frequency;
first and second frequency dividers that divide the frequency at a second frequency division ratio, and output one of the output signals of the first and second frequency dividers according to the state of the modulated signal. first and second charging circuits that output first and second charging currents; first and second discharge circuits through which first and second discharge currents flow; Based on the output signal and the state of the modulated signal, connect one of the first and second charging circuits or the first and second discharging circuits to the capacitor, and connect both ends of the capacitor. 1. A modulation circuit comprising: control means for generating a trapezoidal voltage; and a low-pass filter for extracting a fundamental wave component from the trapezoidal voltage appearing at both ends of the capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10556085A JPS61264845A (en) | 1985-05-17 | 1985-05-17 | Modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10556085A JPS61264845A (en) | 1985-05-17 | 1985-05-17 | Modulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61264845A JPS61264845A (en) | 1986-11-22 |
| JPH0353824B2 true JPH0353824B2 (en) | 1991-08-16 |
Family
ID=14410926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10556085A Granted JPS61264845A (en) | 1985-05-17 | 1985-05-17 | Modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61264845A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005286774A (en) * | 2004-03-30 | 2005-10-13 | Sanyo Electric Co Ltd | Transmission signal generating device |
-
1985
- 1985-05-17 JP JP10556085A patent/JPS61264845A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61264845A (en) | 1986-11-22 |
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