JPH0353834B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field of the Invention] The present invention relates to a color encoder circuit that obtains a video signal compatible with an NTSC or PAL television receiver from three primary color signals. [Problems to be solved by the invention] Generally, the color encoder circuit used in personal computers, game machines, etc. uses a circuit as shown in Fig. 4, and is NTSC or
It is compatible with PAL television receivers. In the figure, 5 is a matrix circuit, which is formed from inverters 60, 61, 65-67, buffers 62-64, and resistors 68-75, and inputs three primary color signals from input terminals 1, 2, and 3.
Burst flag signals are inputted from the input terminals 4, respectively, to obtain color difference signals (B-Y) and (R-Y).
These color difference signals are modulated in quadrature modulators 6, 7 by color subcarrier signals obtained via a phase shift circuit 12. The phase of the modulated color difference signal (R-Y) from the quadrature modulator 7 is inverted by a switch circuit 76 at a cycle twice that of the horizontal synchronizing signal supplied from the input terminal 8, and the signal is output as a PAL chroma output. obtained,
It also forms a color encoder circuit that obtains chroma output compatible with NTSC television receivers without inversion. Therefore, PAL method and
The means to obtain chroma output compatible with NTSC receivers is by using signals after quadrature modulation, and analog switches with excellent frequency characteristics are used to switch signals in the high frequency band (4.43MHz). The disadvantage is that it is necessary and expensive.
Furthermore, the phase inversion of the color difference signal (R-Y) cannot always be said to be good. [Object of the Invention] The present invention was made in view of the above-mentioned problems, and its main purpose is to provide PAL in a relatively low frequency band.
The object of the present invention is to provide a color encoder circuit equipped with a matrix circuit for obtaining color difference signals compatible with television receivers of the NTSC and NTSC systems. Another object of the present invention is to provide a color encoder circuit equipped with a matrix circuit that obtains color difference signals without fluctuations in DC components when switching to obtain color difference signals compatible with PAL and NTSC receivers. . Still another object of the present invention is to provide a color encoder circuit that can be easily integrated into a semiconductor integrated circuit. [Summary of the Invention] The color encoder circuit of the present invention has a matrix circuit section that generates color difference signals at twice the period of the horizontal synchronization signal by using a circuit system that obtains color difference signals (B-Y) and selection using a switching signal. It is possible to obtain a chroma output compatible with PAL and NTSC television receivers by providing a circuit system that obtains an output that inverts the phase of the signal (R-Y) or an output that does not invert the phase. This is a characteristic feature. [Embodiments of the Invention] Regarding the color encoder circuit of the present invention, the first embodiment
This will be explained based on FIGS. 3 to 3. FIG. 1 is a block diagram of a color encoder circuit, in which a matrix circuit 5 has input terminals 1, 2, and 3.
The three primary color signals R, G, and B are supplied from the input terminal 4, and the burst flag signal is supplied from the input terminal 4, respectively. From terminal 8, flip-flop (hereinafter abbreviated as F/F) 9
An inverted horizontal synchronization signal is supplied. A color subcarrier signal is supplied from a terminal 11 to a phase shift circuit 12 . 6 and 7 are quadrature modulation circuits. The switch circuit 10 is NTSC or PAL.
This is a switch for selecting a method. A signal with a cycle twice that of the horizontal synchronizing signal supplied to the matrix circuit 5 is controlled by the switch circuit 10,
In the case of a PAL system receiver, the matrix circuit 5 obtains an output in which the phase of the color difference signal (B-Y) and the horizontal synchronization signal are inverted at a period twice that of the horizontal synchronization signal. In this case, the color difference signal (B-
Y) and (RY). These color difference signals are supplied to quadrature modulation circuits 6 and 7, respectively, and a color subcarrier signal inputted from a terminal 11 is processed by a phase shift circuit 12 into a signal with a π/4 phase lead and a π/4 phase delay. The signals are quadrature-modulated, and the modulated color difference signals are superimposed to obtain a chroma output. Now, FIG. 2 is a circuit diagram showing an embodiment of the matrix circuit portion of the color encoder circuit of the present invention. The matrix circuit 5 shown in FIG. 2 is formed from a circuit that obtains outputs of the (B-Y) system and (R-Y) system of color difference signals. Terminals 1 to 4 are connected to inverters 20 and 21 and buffers 22 and 23, respectively, their output terminals are connected to resistors 39 to 42, and their other ends are commonly connected and connected to the connection point of resistors 48 and 49. is connected to the output terminal 17 to form a (B-Y) system circuit for color difference signals. On the other hand, in the color difference signal (R-Y) circuit system, the Q terminal of the F/F 9 is connected to one terminal of the NAND circuits 24, 27, 29 and one terminal of the AND circuit 31.
The terminals of F/F9 are connected to NAND circuits 25, 26,
It is connected to one terminal of terminals 28 and 30. Input terminal 1 is connected to the other input terminal of NAND circuit 24 and is connected via inverter 32.
connected to the other input terminal of the NAND circuit 25;
The output terminals of NAND circuits 24 and 25 are wired
An OR circuit (hereinafter abbreviated as W-OR circuit) 36 is formed and connected to a resistor 43. Also, terminals 2 and 3
A logic circuit is formed with the same connection as terminal 1. The terminal 4 is connected to one input terminal of the NAND circuit 35, the other input terminal of the NAND circuit 35 is connected to the P terminal of the F/F 9 and the switch circuit 10, and its output terminal is connected to the NAND circuit 30 and the AND circuit 31. and the other terminal, and their respective output terminals are connected to resistors 46 and 47. The other ends of the resistors 43 to 47 are commonly connected, and are also connected to the common connection point of the resistors 50 and 51 and the output terminal 18. Next, the operation will be explained based on the timing charts shown in FIGS. 3a to 3j. First, a color difference signal (B-Y) system circuit that operates in common in both the PAL system and the NTSC system will be described. Three primary color signals R, G, B and a burst flag signal as shown in FIG. 3 a to d are inputted to input terminals 1 to 4, respectively, and an inverted horizontal synchronization signal shown in FIG. 3 e is input to terminal 8. Supplied. Therefore,
When the pulses shown in Fig. 3 a to d are supplied, (B-Y)
system inverters 20, 21 and buffers 22, 2
The logical value of the output of 3 is as shown in Table 1. Furthermore, the inverters 20, 21 and the buffers 22, 23 are open collectors, and the resistance values of the resistors 39 to 42 are such that the resistance value of the resistor 39 is the largest, and the resistance value of the resistor 42 is the largest.
Weighting is given to small values such as 0 and 41.

[Table] When the output state is as shown in Table 1, the buffer 23
Depending on the timing of the burst flag signal applied to terminal 1, the (B-Y) signal is offset to the negative side to generate a color burst signal, and
7 to color difference signals (B-Y) as shown in Fig. 3 h.
output pulses are obtained. Next, (R-Y) in the case of an NTSC receiver
The operation of the system circuit will be explained. Input terminal 1~
Similarly to the above example, pulses as shown in FIGS. 3a to 3d are inputted to input terminal 4, and an inverted horizontal synchronizing signal shown in FIG. 3e is inputted to input terminal 8. The switch 10 is connected to a terminal 14 in order to support the NTSC system. Therefore, the P terminal of F/F9 is grounded, and the output of the Q terminal is "1" and the output of the terminal is "0" as shown in Fig. 3 f-1 and g-1.
becomes. That is, one terminal of the NAND circuit 30 is fixed to "0", and one terminal of the AND circuit 31 is fixed to "1". On the other hand, one terminal of the NAND circuit 35 is fixed to "0", and even if the other terminal receives "1" or "0" of the burst flag signal shown in FIG.
The output of the circuit 35 is fixed at "1", the output terminal of the NAND circuit 30 becomes "1", and the output terminal of the AND circuit 31 becomes "0". NAND circuit 30 and
The output terminal of the AND circuit 31 is formed of an open collector, and the resistance values of the resistors 46 and 47 are set to be equal, so that the influence of the burst flag signal is eliminated. In addition, the three primary color signals R,
G, B and burst flag signals are input as shown in FIG. 3 a to d, and the third
The outputs shown in Figures f-1 and g-1 are input. Therefore, the output states of the W-OR circuits 36, 37, and 38 are as shown in Table 2.

[Table] The resistors 43, 44, and 45 are weighted so that their resistance values increase sequentially, and the output terminal 18 outputs a color difference signal (R-
Y) is output. Next, the case of PAL system will be explained. The switch 10 switches to the contact 13. F/F9 P
When a high level signal is input to the terminal, output pulses as shown at f-2 and g-2 in FIG. 3 are input to the Q terminal and the terminal. (RY) system output terminal 18
, the output as shown in FIG. 3j is obtained. When the Q terminal is "1" and the terminal is "0" period,
Since the output waveform is the same as in the case of the NTSC method, the creation of a logic value table is omitted. In the next cycle, when the Q terminal of F/F9 is reversed to "0" and the terminal to "1",
The output states of the W-OR circuits 36, 37, and 38 are as shown in Table 3.

〔Effect of the invention〕

The present invention is a color encoder circuit that can obtain color difference signals compatible with PAL and NTSC television receivers using a matrix circuit. By inverting at twice the period, a color difference signal compatible with the PAL system can be obtained very easily. Therefore, since signals can be inverted in a relatively low frequency band (approximately 1 MHz), an inexpensive color encoder circuit can be provided without using expensive analog switches compared to conventional color encoder circuits. The color encoder circuit of the invention can be easily integrated into a semiconductor integrated circuit. Furthermore, even if the chroma output of the NTSC system is switched to the PAL system, the DC output of the color difference signal (R-Y) system is kept constant, so there is no distortion in the video signal, resulting in an excellent effect. It is something that plays.

[Brief explanation of drawings]

FIG. 1 is a book diagram showing an embodiment of the color encoder circuit of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the matrix circuit which is the main part of the color encoder circuit of the present invention, and FIG. 3 is a book diagram showing an embodiment of the color encoder circuit of the present invention. FIG. 4 is a diagram showing a timing chart for explaining the operation of the color encoder circuit of the invention, and FIG. 4 is a diagram for explaining the conventional color encoder circuit. 1, 2, 3: Input terminal to which three primary color signals are input, 4: Input terminal to which burst flag signal is input, 5: Matrix circuit, 6, 7: Quadrature modulation circuit, 8: Input to which horizontal synchronization signal is input. terminal,
9: F/F, 11: Color subcarrier signal input terminal, 10: Switch circuit, 12: Phase shift circuit,
15: Output terminal.

Claims (1)

[Claims] 1 A matrix circuit consisting of a first circuit system that obtains a first color difference signal (B-Y) from the three primary color signals and a second circuit system that obtains the second color difference signal (R-Y) from the three primary color signals. By supplying the first switching signal to the flip-flop circuit, pulses having a period twice that of the horizontal synchronizing signal and whose phases are inverted from each other are sent from the flip-flop circuit to the first switching signal of the matrix circuit. The second color difference signal (R-Y) is supplied to the second circuit system and is compatible with the PAL system.
At the same time, the logic signals fixed at "1" and "0" from the output terminals of the flip-flop circuit are transferred to the second circuit system of the matrix circuit by a second switching signal. A third color difference signal compatible with the NTSC system is supplied to
-Y), and supplies the first and second or third color difference signals obtained from the matrix circuit to the first and second quadrature modulation circuits, respectively, to quadrature modulate color subcarriers having different phases. A color encoder circuit characterized in that the respective outputs are superimposed to obtain a chroma output compatible with the NTSC system and the PAL system.