JPH0354059U - - Google Patents
Info
- Publication number
- JPH0354059U JPH0354059U JP11407589U JP11407589U JPH0354059U JP H0354059 U JPH0354059 U JP H0354059U JP 11407589 U JP11407589 U JP 11407589U JP 11407589 U JP11407589 U JP 11407589U JP H0354059 U JPH0354059 U JP H0354059U
- Authority
- JP
- Japan
- Prior art keywords
- data
- input
- fifo memory
- output
- detects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002401 inhibitory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Computer And Data Communications (AREA)
Description
第１図は本考案の通信制御装置の一実施例のブ
ロツク図、第２図は第１図の実施例の動作を説明
するためのタイミングチヤートである。
１……ＣＰＵ、２……Ｉ／Ｏ機器、３……ＦＩ
ＦＯメモリ、４……入力ハンドシエイク、５……
出力ハンドシエイク、６……入力カウンタ、７…
…出力カウンタ、８……フリツプフロツプ、９…
…アンドゲート、ＣＤＯＵＴ……データ書込み要
求、ＣＡＣＫ……アクノレツジ信号、ＩＳ……イ
ンプツトストローブ信号、ＩＲ……インプツトレ
デイ信号、ＯＲ……アウトプトレデイ信号、ＯＳ
……アウトプツトストローブ信号、ＩＮＨ……禁
止（インヒビツト）信号。
FIG. 1 is a block diagram of an embodiment of the communication control device of the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1...CPU, 2...I/O equipment, 3...FI
FO memory, 4... Input handshake, 5...
Output handshake, 6... Input counter, 7...
...Output counter, 8...Flip-flop, 9...
...AND gate, CDOUT...data write request, CACK...acknowledge signal, IS...input strobe signal, IR...input ready signal, OR...output ready signal, OS
...Output strobe signal, INH...Inhibit signal.
Claims (1)
る通信制御装置であつて、 ＣＰＵからのシリアルデータを受信して一時的
に記憶した後、入出力機器へ順次出力するＦＩＦ
Ｏメモリ３と、 該ＦＩＦＯメモリへのデータ書込みが行われる
毎に、ＣＰＵに対してＦＩＦＯメモリへの書込み
終了を示すアクノレツジ信号ＣＡＣＫを出力する
手段４，９と、 ＦＩＦＯメモリへの書込みデータ数をカウント
し、最終のデータの書込みが完了したことを検出
する入力カウンタ６と、 ＦＩＦＯメモリに蓄積されたデータの読出しデ
ータ数をカウントし、最終データの読出しが完了
したことを検出する出力カウンタ７と、 前記入力カウンタによりＦＩＦＯメモリへの最
終データ書込み完了が検出されてから前記出力カ
ウンタにより最終データの読出しが完了したこと
が検出されるまでの間、前記アクノレツジ信号の
出力を禁止する手段８とを有する通信制御装置。[Scope of claim for utility model registration] A communication control device that controls data communication from a CPU to input/output devices, which receives serial data from the CPU, temporarily stores it, and then sequentially outputs it to the input/output devices. FIF
an O memory 3; means 4 and 9 for outputting an acknowledge signal CACK indicating completion of writing to the FIFO memory to the CPU each time data is written to the FIFO memory; an input counter 6 that counts and detects that writing of the final data is completed; and an output counter 7 that counts the number of read data of the data stored in the FIFO memory and detects that reading of the final data is completed. , means 8 for inhibiting output of the acknowledge signal from when the input counter detects completion of writing the final data to the FIFO memory until the output counter detects completion of reading the final data; Communication control device with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11407589U JPH0354059U (en) | 1989-09-28 | 1989-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11407589U JPH0354059U (en) | 1989-09-28 | 1989-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0354059U true JPH0354059U (en) | 1991-05-24 |
Family
ID=31662464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11407589U Pending JPH0354059U (en) | 1989-09-28 | 1989-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0354059U (en) |
-
1989
- 1989-09-28 JP JP11407589U patent/JPH0354059U/ja active Pending
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