JPH0354380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device in an information processing device, and more particularly to a memory access control device that controls continuous access to data consisting of one or more elements.

[Conventional technology]

Conventionally, the present inventor developed a memory access control device in December 1982 that controls continuous access to data consisting of multiple elements such as vector data.
The name of the invention is ``Memory Access Control Device'' as described in Japanese Patent Application No. 58-234486 filed on May 13th. This proposed memory access control device has memory unit address information of the first element,
For example, from the bank address and the number of elements, the address information of the memory unit of the last element of the data to be accessed in advance is obtained and held, and the address information of the memory unit of the first element of the subsequent data to be accessed is stored. The number of clock cycles from the start of accessing the subsequent data until the memory unit of the last element of the preceding data is accessed is calculated from the difference between the address information of the memory unit of the last element of the preceding data, and the memory unit is calculated. By comparing the cycle time of , and the number of clock cycles obtained, it is found that the same memory unit is not accessed within the cycle time of the memory unit in the subsequent data access and the previous data access, so By calculating the waiting time from the end of access to the start of access to subsequent data, control is performed so that data consisting of multiple elements can be accessed continuously at high speed.

[Problem that the invention seeks to solve]

However, in an information processing device in which the number of elements that can be simultaneously accessed to the memory is variable, the conventional memory access control device as described above controls the memory unit of the last element of the preceding data after starting access to subsequent data. The number of cycles until access varies depending on the number of elements that can be accessed at the same time, and the number of waiting cycles required may be larger than the actually required number of waiting cycles, causing performance deterioration, or the number of waiting cycles that are actually required may be There are drawbacks such as the number of waiting cycles being smaller than the number of cycles, or the number of waiting cycles being determined becoming invalid, which reduces the efficiency of hardware usage. For example, when there are multiple arithmetic units and data is transferred from memory to all the arithmetic units at the same time, one arithmetic unit malfunctions, and the data containing the malfunctioning arithmetic unit or the malfunctioning arithmetic unit In an information processing device in which a plurality of arithmetic units are separated and degenerated to perform operations, it is necessary to make the number of elements that can be accessed simultaneously variable, and this drawback is quite possible.

[Means for solving problems]

The memory access control device of the present invention is composed of a plurality of memory units that can be accessed independently of each other, and each of them has one or more memory units arranged consecutively on the memory, and the memory is arranged in the order of the memory units. A memory access control device for controlling access to data consisting of elements, the element number supply means supplying the number of data elements;
address information supply means for supplying address information in memory units of the first element; and address information calculation means for calculating address information in memory units for the last element from the number of elements of the data and address information in memory units for the first element; , holding means for holding memory unit address information of the final element; address information of the memory unit of the final element of the first data held in the holding means;
difference calculation means for calculating the difference between the first element of the second data accessed subsequently to the memory unit address information, and the difference calculation means using a mode signal that specifies the number of elements that can be accessed at the same time. a correction means for correcting the difference in address information calculated by the correction means; and a first correction means for correcting the difference in address information calculated by the correction means;
Even if you start sending a second data access request after sending a second data access request, the memory unit that is in use due to the first data access will not be able to access the second data. It is characterized in that it includes calculation means for calculating a time interval for not being accessed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a memory access control device according to the present invention. In the figure, the memory access control device of this embodiment includes an adder circuit 1, a register 2, a subtracter circuit 3, a gate circuit 4, a shift circuit 5, a subtracter circuit 6, and a gate circuit 7.

The adder circuit 1 receives the bank address of the leading element of the data supplied via the connection 101 and the connection 102.
The bank address of the last element of the data is calculated by adding the number of data elements supplied via the addition result and subtracting the value "1" from the addition result, which is then supplied to the register 2 via the connection 103.

Register 2 holds the bank address of the final element of data that is the output of adder circuit 1, and the contents thereof are supplied to subtracter circuit 3 via connection 104.

The subtraction circuit 3 extracts the data from the bank address of the final element of the data supplied via the connection 104.
1, and calculate their difference by subtracting the bank address of the first element of the data supplied through connection 10.
5 to the gate circuit 4. here,
The bank address of the last element and the bank address of the first element of the data supplied to the subtraction circuit 3 are not the bank addresses of the last element and the first element of the same data, but the bank address of the last element is the bank address of the data accessed in advance. Note that the bank address of the last element of is the bank address of the last element, and the bank address of the first element is the bank address of the first element of the data that is accessed subsequent to the preceding data including the last element.

The gate circuit 4 calculates the difference between the bank address of the last element of the preceding data supplied via the connection 105 and the bank address of the first element of the subsequent data, based on the memory bank number information supplied via the connection 106. The signal is masked and supplied to the shift circuit 5 via the connection 107. In this embodiment, it is assumed that there are three modes for the number of memory banks: 256 banks, 128 banks, and 64 banks. In the case of 256 banks, all bits given by connection 105 are valid, and in the case of 128 banks, all bits given by connection 105 are valid. suppresses the most significant bit given by connection 105 to “0”, and in case of 64 banks, connection 1
The gate circuit 4 is controlled so that the upper two bits given by 05 are suppressed to "0".

The shift circuit 5 transfers the masked bank address difference supplied via the connection 107 to the connection 10.
The signal is shifted to the right according to information on the number of arithmetic pipelines supplied via line 109 and supplied to subtraction circuit 6 via connection 109 . In this example, there are three modes for the number of calculation pipelines: 4, 2, and 1, and it is assumed that 4 elements can be accessed simultaneously and 2 elements can be accessed simultaneously. , 4
The shift circuit 5 performs control such that if there is a book, it is shifted by two bits to the right, if there are two, it is shifted by one bit to the right, and if there is one, it is not shifted.

Subtraction circuit 6 extracts the memory bank cycle time information from connection 109 from the memory bank cycle time information provided by connection 110.
The difference in the shifted bank address supplied via the circuit 111 is applied to the gate circuit 7 via the connection 111.

The gate circuit 7 sets the output of the subtraction circuit 6 to all bits "0" when the output of the subtraction circuit 6 supplied via the connection 111 is negative, that is, when the sign bit of the subtraction circuit 6 is "1". , is output via connection 112, and the value of connection 112 is obtained as the number of waiting cycles.

Note that in this embodiment, the number of memory banks is the maximum.
256, so the connections 101, 103, 104,
105, 107, 109, and 111 are all 8 bits wide. Further, it is assumed that the maximum possible value of the number of data elements is 256 when the number of calculation pipelines is four, 128 when there are two, and 64 when there is one. Therefore, the connection 102 that supplies the number of elements of data is also 8 bits wide. It is also assumed that the memory bank cycle time is 16 clock cycles. Therefore, connection 110, which provides memory bank cycle time information, is also represented as 8 bits wide.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the time charts of FIGS. 2, 3, and 4. Here, Figure 2 shows an example where the number of calculation pipelines is 4 and the number of memory banks is 256.
Figure 3 shows that the number of calculation pipelines is two, and the memory
An example in which the number of banks is 256, and Figure 4 is an example in which the number of calculation pipelines is 4 and the number of memory banks is 128. 256, and in FIG. 3, both the preceding data and the succeeding data are 128.

In the example of FIG. 2, the bank address of the leading element of the preceding data is "0", and the bank address of the leading element of the succeeding data is "193". First, when an access request for preceding data is issued, the bank address "0" of the first element supplied via the connection 101 and the number of elements "256" supplied via the connection 102 are added in the adder circuit 2. , the value "1" is further subtracted and taken into register 2.
That is, the bank address "255" of the final element of the preceding data is held in register 2, and this value is held until an access request for subsequent data is issued.

When a subsequent data access request is issued, the subtraction circuit 3 selects the bank address “255” of the last element of the preceding data held in the register 2 and the bank address “255” of the first element of the subsequent data supplied via the connection 101. The difference from address "193" is "62", that is, "00111110" is calculated in binary representation.

When the number of memory banks is 256, no operation is performed in the gate circuit 4, and when the number of arithmetic pipelines is 4, the shift circuit 5 shifts 2 bits to the right. "00001111" or the value "15" is supplied in binary representation. This value indicates that an access request for an element of subsequent data will be sent to the bank for which an access request was sent in the last cycle of the preceding data, 15 clock cycles after the start of sending a request to access memory for subsequent data. It means to be done.

The subtraction circuit 6 receives the value "15" from the memory bank cycle time "16" supplied via connection 110.
Subtract , and get the difference "1". Since this value "1" is not a negative number, nothing is done in the gate circuit 7, and it is outputted via the connection 112 as the number of waiting cycles. That is, in this example, if the wait time is longer than one clock cycle, there will be no bank conflict between the preceding data access and the subsequent data access.

Referring to FIG. 2, among the banks that are accessed the first time for subsequent data, banks 193 to 195 are in the used state in 16 cycles from timing _T48 to timing _T63 , and bank 196 is in the used state. Since this is the cycle from timing T ₄₉ to timing T ₆₄ , if accessing subsequent data starts after the cycle timing T ₆₅ , it will access the bank that is in use by accessing the preceding data. is not accessed.
Timing when access to preceding data ends
Since it is a cycle of T ₆₃ , the timing is just right.
Access to subsequent data can be started after waiting for one cycle of _T64 .

Next, in the example of FIG. 3, the bank address of the leading element of the preceding data is "128", and the bank address of the leading element of the succeeding data is "193". Similar to the example shown in FIG. 2, when an access request for preceding data is issued, in addition circuit 1
The bank address of the final element is “255” from the bank address of the first element “128” supplied via the connection 102 and the number of elements “128” supplied via the connection 102.
is calculated and loaded into register 2.

When a subsequent data access request is subsequently issued, the subtraction circuit 3 selects the bank address "255" of the last element of the preceding data held in the register 2 and the bank address of the first element of the subsequent data supplied through the connection 101. Difference “62” from address “193”
That is, "00111110" is calculated in binary representation.

Since the number of memory banks is 256, the gate circuit 4 does nothing. In addition, since the number of calculation pipelines is two, in the shift circuit 5, the difference "62" between the bank address of the last element of the preceding data obtained by the subtraction circuit 3 and the bank address of the first element of the subsequent data is shifted to the right. Shifted by one bit, the subtraction circuit 6 is supplied with "00011111" in binary representation, ie, the value "31", via a connection 109.

The subtraction circuit 6 subtracts the value "31" from the memory bank cycle time "16" supplied via the connection 110 to obtain "-15" which is supplied to the gate circuit 7, but since it is a negative number, It is set to "0" by the gate circuit 7 and outputted as the waiting cycle number via the connection 112. That is, in this example, even if access to subsequent data is started without waiting after access to preceding data is completed, bank conflict between access to preceding data and access to subsequent data will not occur.

Referring to FIG. 3, the bank 193 that is accessed in the first cycle of subsequent data is in the used state due to the access of preceding data in the cycle from timing T ₃₂ to timing T ₄₇ .
Since the bank 194 is in the used state due to the access of the preceding data in the cycle from timing T ₃₃ to timing T ₄₈ , if the access of the subsequent data starts after the cycle of timing T ₄₉ , it will be accessed as the access of the preceding data. There is no bank conflict between the two. Since the access to the preceding data ends at timing T ₆₃ , the access to the subsequent data ends at timing T ₆₄ without waiting.
It is possible to start from the cycle of

Finally, in the example of FIG. 4, the bank address of the leading element of the preceding data is set to "0", and the bank address of the leading element of the succeeding data is set to "65". When an access request for preceding data is issued, the adder circuit 1 calculates the value "255" from the bank address "0" of the leading element supplied via the connection 101 and the number of elements "256" supplied via the connection 102. ” is obtained and taken into register 2. Here, since the number of memory banks is 128, the bank address of the final element of the preceding data is the value “127” modulo 128.
However, since adder circuit 1 and register 2 have a width of 8 bits, the value "255" is taken into register 2.

Subsequently, when a subsequent access request is issued, the subtraction circuit 3 changes the bank address of the first element of the subsequent data supplied via the connection 101 from the value "255" held in the register 2 to "65".
is subtracted, and the difference "190", that is, "10111110" in binary notation is supplied to the gate circuit 4.

Since the number of memory banks is 128, gate circuit 4
Then, the most significant bit of the 8-bit data supplied via connection 105 is set to "0". In this case, the output “190” of the subtraction circuit 3 is transferred to the gate circuit 4.
is the binary representation “00111110” with the most significant bit set to “0”, that is, “62”, and the shift circuit 5
is supplied to Furthermore, since the number of arithmetic pipelines is four, the value "62" supplied via the connection 107 is shifted to the right by two bits in the shift circuit 5, and the value "15" is supplied to the subtraction circuit 6.

As in the example of FIG. 2, the subtraction circuit 6 outputs the value "1", and the gate circuit 7 outputs the waiting cycle number "1" via the connection 112.

Referring to FIG. 4, memory banks accessed in the first cycle of subsequent data are accessed in banks 65 to 67 by access of preceding data in cycles from timing T ₁₆ to timing T ₃₁ and from timing T ₄₈ to timing T _63. The cycle of bank 68 is timing T ₁₇ or timing
Since the cycle of T ₃₂ and the cycle of timing T ₄₉ to timing T ₆₄ are each in the used state, accessing the subsequent data starts from the cycle of timing T ₆₅ and becomes the used state by accessing the preceding data. Banks that are currently in use will not be accessed. The access to the preceding data ends in the cycle of timing T ₆₃ , so the timing
If one cycle of _T64 is waited, there will be no bank contention between the preceding data access and the subsequent data access.

In this embodiment, although the case where the number of calculation pipelines is one is not mentioned, the operation can be easily understood from the above explanation.

〔Effect of the invention〕

As explained above, according to the present invention, the address information of the last element of the first data that is accessed in advance and the address of the first element of the second data that is accessed subsequent to the first data By providing a correction means that corrects the difference in information using a mode signal that specifies the number of elements that can be accessed simultaneously, even if the number of elements that can be accessed simultaneously is variable, the information can be corrected after sending the first data access request. The time interval until the sending of the second data access request can be started can be calculated very precisely, which has the effect of improving hardware usage efficiency and effective performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a memory access control device according to the present invention, and FIG.
FIGS. 3 and 4 are time charts showing an example of the operation of the present invention, respectively. 1... Addition circuit, 2... Register, 3... Subtraction circuit, 4... Gate circuit, 5... Shift circuit, 6
...Subtraction circuit, 7...Gate circuit, 101-11
2...Connection.

Claims (1)

[Claims] 1. Consisting of a plurality of memory units that can be accessed independently of each other, each of which consists of one or more elements consecutively arranged in a memory that is addressed in the order of the memory units. A memory access control device for controlling data access, comprising: element number supply means for supplying the number of data elements;
address information supply means for supplying address information in memory units of the first element; and address information calculation means for calculating address information in memory units for the last element from the number of elements of the data and address information in memory units for the first element; , holding means for holding memory unit address information of the final element; address information of the memory unit of the final element of the first data held in the holding means;
difference calculation means for calculating the difference between the first element of the second data accessed subsequently to the memory unit address information, and the difference calculation means using a mode signal that specifies the number of elements that can be accessed at the same time. a correction means for correcting the difference in address information calculated by the correction means; and a first correction means for correcting the difference in address information calculated by the correction means;
Even if you start sending a second data access request after sending a second data access request, the memory unit that is in use due to the first data access will not be able to access the second data. 1. A memory access control device, comprising calculation means for calculating a time interval for not being accessed.