JPH0354463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing field effect transistors and semiconductor devices such as integrated circuits including the field effect transistors.

In order to improve the performance of semiconductor devices, the processing accuracy of pattern dimensions is required to be in the submicron range. However, with conventional photolithography technology, the practical limit is 1 μm or more, and self-alignment technology is used as a means to break this limit. Conventional self-alignment technology for manufacturing GaAs field effect transistors involves forming a gate metal such as W or Mo in advance, processing it into a T-shaped cross-section, and then forming the source and drain metal layers. Ta. The disadvantages of this were high gate resistance and incomplete heat resistance up to 850°C.

An object of the present invention is to provide a method for manufacturing a semiconductor device using self-alignment technology with excellent heat resistance.

Hereinafter, one embodiment of the present invention will be explained in detail with reference to FIG.

FIG. 1 is a diagram showing the manufacturing process of a field effect transistor using a GaAs semiconductor.

An n-type active layer 11 is created by implanting Si ions into a required portion of the semi-insulating GaAs substrate 1. Next, the first layer of silicon oxide film 2 is applied to the GaAs surface, and the second layer is
A silicon nitride film 3 as a layer and a silicon oxide film 4 as a third layer are laminated in order. Next, a desired resist pattern 5 is formed using photolithography technology.
is formed, and unnecessary portions of the silicon oxide film and silicon nitride film are removed by dry etching using this resist pattern as a mask. In this process, the second layer of silicon nitride film 3 is intentionally side-etched to make it shorter than the dimensions of the first and third layers, so that the cross-sectional shape of the laminated film becomes an E-shape. Next, high-concentration Si was implanted using the processed pattern as a mask, and after removing the resist film 5, the sample was heat-treated at a temperature of 850°C ^.
A layer 21 is formed (see a). Next, Au,
Ohmic metals containing Ge as the main component 15, 16
is deposited vertically on the sample, heat-treated at 400°C to remove the ohmic, and form source and drain electrodes (Figure b). Subsequently, polysilicon 25 and 26 are applied to the sample from multiple directions (FIG. 3(c)). After that, after lightly etching the polysilicon 25 from the top surface to improve separation, only the silicon nitride 3 is removed by etching, leaving unnecessary metal 1.
6 and 26 are excluded. Subsequently, only the silicon oxide 2 is removed to expose the n-type active layer 11. Subsequently, gate metals 35 and 36 such as Al are deposited in the vertical direction (d in the same figure) to create a gate electrode of a shotgun junction. As a result, the polysilicon 25 determines the gate length, and the gate is self-aligned between the source and drain. Thereafter, the unnecessary metal 36 is removed by etching polysilicon, and a field effect transistor is fabricated.

In the above embodiment, the combination of the first to third layers to obtain an E-shaped cross-sectional shape was described, but any combination of materials may be used to achieve the same purpose, such as Mo, Ti, which has excellent heat resistance. , W, Cr and other metals, Si, Ge
Membranes are also available. Further, in the above embodiment, polysilicon was used as the material for determining the gate length, but it should be noted that the above-mentioned materials or organic materials such as Al and resist materials can also be used depending on the combination of the first to third layers. It should also be noted that the third layer 4 may be removed before depositing polysilicon in the manufacturing procedure described in the above embodiments.

In view of the spirit of the present invention, at least three layers are used to obtain the E-shaped cross-sectional shape, but it goes without saying that the structure may be composed of three or more layers.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of a field effect transistor according to an embodiment of the present invention.

Claims (1)

[Claims] 1. In a method for manufacturing a field effect transistor,
A first layer is placed on the area where the gate electrode is to be formed on the semiconductor substrate.
a step of forming a layer film and a second layer film smaller in dimension in the source/drain direction than the first layer film and existing inside in the stacking order of the first layer film and the second layer film; a step of forming a source and a drain using a mask as a mask; a step of forming a layer, a step of removing the second layer film, and a step of removing the first layer film after the step,
A method for manufacturing a semiconductor device, comprising the steps of: forming a gate using the first layer as a mask; and removing the first layer. 2 The formation of the first layer film and the second layer film includes a step of depositing the materials of the first layer film and the second layer film on the entire surface of the semiconductor substrate, and a step of depositing the material of the third layer film after the step. a step of depositing a resist after the step, a step of patterning the resist, a step of patterning the three deposited layers using the resist pattern as a mask, and the first layer film and the third layer film. The second layer film is formed by further removing the covering layer of the second layer film material from the side surface using the mask as a mask, and forming the first layer includes applying the material of the layer to the source and drain regions and the second layer film. deposited on the semiconductor substrate including a resist pattern;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the deposited film is cut by a step at the edge of the resist pattern. 3. Manufacturing the semiconductor device according to claim 2, wherein the first layer film, the second layer film, the third layer film, and the first layer are each made of silicon oxide, silicon nitride, silicon oxide, and polysilicon. Method.