JPH0354514B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention automatically adjusts the sample timing of a signal that has a burst clock (hereinafter referred to as a clock run-in signal) with a fixed frequency prior to a data signal, such as a television text multiplex signal. This invention relates to a phase locked circuit suitable for setting the optimum phase. [Technical background of the invention and its problems] Conventionally, the sampling timing of a television multiplexed signal is established using the color subcarrier frequency _sc ( _sc =
This was achieved by creating 8/5 _sc (5.727272MHz) from 3.579545MHz) and synchronizing the frequency-divided signal by 2 with the clock run-in signal using a phase-locked loop. FIG. 1 shows the signal format of television teletext broadcasting in Japan. That is, as shown in FIG.
1 and an information data section 12.
0 is inserted. H is a horizontal synchronization signal, and SC is a color subcarrier. At the beginning of the header section 11 is a clock run-in signal CRI consisting of a fixed pattern signal of 8 clock cycles of 2.863636 MHz as shown in FIGS. 1b and 1c. Note that FC is a framing code. The sample timing must be determined by this clock run-in signal CRI, but even if the phases are matched over 8 cycles, phase synchronization can only be achieved within a rough range, making it difficult to obtain the correct sample timing. It was. If correct sample timing cannot be obtained and the error becomes large, a decoding error will occur in the received signal. FIG. 2 shows the configuration of a conventional phase-locked loop using a clock run-in signal CRI. Color subcarrier frequency sc more than 8/5sc
A clock CK ₀ is generated, which is passed through a tap delay device 27 with an output tap at regular intervals to generate a plurality of clocks whose phases are sequentially shifted by a fixed amount. One of the plurality of clocks is selected by a selector 26, divided by two by a frequency divider 25, and provided to the phase comparator 21 as one input. Further, the clock run-in signal CRI is given to the phase comparator 21 as the other input. The phase comparator 21 is composed of, for example, a multiplier, and outputs a signal in which harmonics are mixed in the phase difference between two signals. This signal is subjected to removal of high frequency components by an appropriate loop filter 22, gain adjusted by an amplifier 23, and then sent to a controller 2.
Sent to 4. This controls the selector 26, and is composed of, for example, an up-down counter.It performs up or down counting in response to the timing signal TC from the timing circuit, and its count output is sent to the selector 26. In such a phase-locked loop, the selector 26 outputs one clock having a predetermined phase relationship with the clock run-in signal CRI. This selected one clock becomes the sample clock SCK through a phase shifter 28 to adjust for the phase difference inherent in the circuit. In principle, a sample clock SCK having a predetermined phase relationship with the clock run-in signal CRI can be obtained with such a loop, but as shown in Figure 1, in the case of a character multiplex signal, the clock run-in signal CRI takes 8 cycles. Since there are only burst signals, it is extremely difficult to establish accurate phase synchronization. In addition, a character multiplex signal is a signal in which one to several lines are superimposed on one field, and when all the clock run-in signals CRI of each field are always in a constant phase relationship with the color subcarrier, the character multiplex signal is Phase synchronization can be corrected sequentially for each superimposed line or for each field, but if the phase relationship of the signals differs for each superimposed line, separate phase synchronization must be performed for each superimposed line, and When the phase of the clock run-in signal CRI differs from that of the color subcarrier, the phase synchronization of the above-mentioned sequential correction cannot be performed. In fact, the character multiplex signal does not necessarily have a fixed phase relationship with the color subcarrier for each field, and when multiple lines of character signals are superimposed on one field, generally the clock line-in signal CRI The phase has a mutually different phase relationship with the color subcarrier.
In addition to this, the phase can also change when, for example, a character signal program is changed. For these reasons, conventionally it has been extremely difficult to establish the sample timing of a character multiplex signal, and it has not been possible to do so with sufficient accuracy. [Object of the Invention] An object of the present invention is to establish phase synchronization between two types of signals, such as a clock line-in signal and a sample clock in a TV text multiplex signal, with sufficient accuracy using only a reference period with a small number of samples. An object of the present invention is to provide a phase-locked circuit that can perform the following steps. [Summary of the Invention] The present invention provides a means for creating at least two comparison signals having the same frequency as an input single-frequency first signal and having phases different from each other by π/2 based on a predetermined original signal. and at least two phase comparison means that respectively compare the phases of at least two comparison signals created by this means and the first signal, and from the comparison results of these phase comparison means, the first signal and the first signal are compared. a calculation means for calculating a phase difference with the original signal and outputting a digital signal including information on the direction and magnitude of the phase shift of the original signal with respect to the first signal; and a means for creating a plurality of second signals having mutually different phases; and a means for creating a plurality of second signals having mutually different phases; The present invention is characterized by comprising a selection means for making a selection based on the output of the calculation means. [Effects of the Invention] According to the present invention, in principle (S/N ratio In good conditions) phase synchronization can be established by a comparison operation within a reference interval of one period of the signal. Therefore, it is particularly suitable for performing phase synchronization between a temporally short clock run-in signal and a sample clock in a television text multiplex signal. [Embodiment of the Invention] FIG. 3 shows a phase locked circuit according to an embodiment of the present invention. In the figure, the first input terminal 31 is connected to the clock run-in signal CRI in the TV character multiplex signal.
(2.863636MHz) is input. This clock run-in signal CRI passes through a band pass filter BPF32 for waveform shaping, and then passes through a phase comparator 33a, 3
It is input to the L terminal of 3b. BPF32 is used as needed to improve performance, and in principle it can be implemented without using it. The signal input to the L terminals of the phase comparators 33a and 33b will be represented by sinx. On the other hand, the second input terminal 40 has a frequency of 8/5sc.
(5.727272MHz) sample clock original signal CK ₀
is input. This signal CK ₀ is the tap delay circuit 4.
1, and clocks CK ₁ , CK ₂ , . . . whose phases are shifted by a fixed amount are created. For example signal CK ₀
When one cycle is divided into 16, the delay device 41 with taps has output taps at intervals of 175/16≈11 nsec. These clocks CK ₁ ,
Two of CK ₂ , CK ₁ and CK ₈ are frequency divider 38
The signals B ₁ =sin(x+), B ₂ =sin(x+−π/
2) and are input to the R terminals of the phase comparators 33a and 33b, respectively. Here, φ is the phase difference between the clock line signal CRI and the signal _CK0 . The frequency dividers 38a and 38b can be realized, for example, with a configuration as shown in FIG. That is, one of two D-flip-flops (such as LS74A) 401 and 402 is used as the frequency divider 38a, and the other flip-flop 402 is used as the frequency divider 38a.
One clock (for example, clock CK ₁ ) and a clock (for example, clock CK ₈ ) having a phase shift of π from that clock are respectively input to the CK input terminal, and one D-flip-flop 4 is used as a clock.
If we divide the frequency by 2 by 01 as sin(x+) and input it to the D input terminal of the other D-flip-flop 402, we will get a signal of sin(x+ -π/2) with a phase shift of π/2. can get. Here, the outputs of the frequency dividers 38a and 38b are almost rectangular waves, so if a sine wave is required, a BPF can be added to this output side. In addition, one flip-flop (frequency divider)
By using only two signals, only signals having mutually opposite phases can be obtained, but signals having phases different from each other by π/2 cannot be obtained. In order to obtain two signals with a phase difference of π/2, one flip-flop is used as each of the frequency dividers 38a and 38b, and these are divided into two signals with a phase difference of π/2.
clock (for example, CK ₁ , CK ₈ ). As will be described later, due to the periodicity of the triangular relationship, the inverse relationship becomes a multivalued function, so if only one phase comparator is used, two types of phase differences can be determined, and only one phase difference can be determined. Therefore, in this example, two phase comparators are provided. The outputs of the phase comparators 33a and 33b are input to comparison result calculation circuits 34a and 34b, where the phase difference, -π/2, is calculated and sent to A/D converters 35a and 35b, respectively. The comparison result calculation circuits 34a and 34b can be realized by the configuration shown in FIG. 5, for example. The harmonic components contained in the outputs of the phase comparators 33a and 33b are filtered through a low-pass filter LPF.
After removing it at 501, the phase comparators 33a, 33
The phase comparator 3 is operated by the arithmetic unit 502 which gives the inverse characteristic of b.
The structure is such that the nonlinear characteristics occurring in 3a and 33b are corrected. That is, the phase comparators 33a, 3
If 3b is configured, for example, by a multiplier, its output will be -cos(2x+)+cos. This signal is filtered through a low-pass filter 501 to generate harmonic components −cos (2x
+) is removed and becomes cos. Since this is the cosine of the phase difference, the arithmetic unit 502 has an inverse cosine relationship.
The phase difference can be found by using something that gives cos ^-1 . In this example, the comparison result calculation circuit 34
Phase comparators 33a, 33 as configurations of a, 34b
b is a multiplier and its inputs are both sine waves, but as another example, the phase comparator 33
When a and 33b are multipliers and their inputs are both rectangular waves, a phase difference can be immediately given to the signal that has passed through the LPF 501. Therefore, at this time, the arithmetic unit 502 that provides the inverse characteristic is not required. At this time, if the signal input to the first input terminal 31 is a rectangular wave, the BPF 32 may be omitted and the signal may be directly input to the L terminals of the phase comparators 33a and 33b.
If this signal is a TV/video signal or a signal received via a transmission line, a rectangular wave shaping circuit 601 consisting of a comparator as shown in FIG. 6 is added after the BPF 32. good. Further, when the outputs of the frequency dividers 38a and 38b are not rectangular waves, a rectangular wave shaping circuit may be added here as well. Set the inverse cosine relation as a single-valued function and set its output range to 0.
cos ^-1 (・) When defined as π (02π)
Table 1 shows the relationship between the phase difference -π/2 calculated by the comparison result calculation circuits 34a and 34b and the actual phase difference -π/2.

【table】

Claims (1)

[Claims] 1. Means for creating at least two comparison signals having the same frequency as an input single-frequency first signal and having phases different from each other by π/2, based on a predetermined original signal. , at least two phase comparison means for respectively comparing the phases of at least two comparison signals created by this means and the first signal; and from the comparison results of these phase comparison means, the first signal and the first signal are compared. calculation means for calculating a phase difference with the original signal and outputting a digital signal including information on the direction and magnitude of the phase shift of the original signal with respect to the first signal; and a means for creating a plurality of second signals having mutually different phases; and a means for creating a plurality of second signals having mutually different phases; A phase-locked circuit comprising: selection means for selecting based on the output of the calculation means. 2 The first signal is a reference signal with a specific pattern added to the data signal, the original signal is a signal with twice the frequency of this reference signal, and the second signal has the same frequency and phase as this original signal. are clock signals that are sequentially shifted by a predetermined amount, and the selection means selects the only clock signal among these clock signals having a predetermined phase relationship with the reference signal based on the output of the calculation means for sampling the data signal. 2. A phase synchronized circuit according to claim 1, which is selected as a sample clock. 3. The phase locked circuit according to claim 1, wherein the original signal is a signal with the same frequency as the first signal, and the second signal is a signal with the same frequency as the original signal. 4. The phase locked circuit according to claim 1, wherein the phase comparison means includes a multiplier. 5. The phase locked circuit according to claim 1, wherein the calculation means includes means for removing high-frequency components. 6. The phase-locked circuit according to claim 1 or 5, wherein the calculation means imparts a transfer characteristic opposite to a transfer characteristic of the phase comparison means to the comparison result of the phase comparison means. 7. The phase synchronization circuit according to claim 4, wherein at least one of the first signal and the comparison signal input to the phase comparison means is a rectangular wave.