JPH0354882A - High resistance semiconductor layer-buried semiconductor laser - Google Patents
High resistance semiconductor layer-buried semiconductor laserInfo
- Publication number
- JPH0354882A JPH0354882A JP13952289A JP13952289A JPH0354882A JP H0354882 A JPH0354882 A JP H0354882A JP 13952289 A JP13952289 A JP 13952289A JP 13952289 A JP13952289 A JP 13952289A JP H0354882 A JPH0354882 A JP H0354882A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- doping
- semiconductor layer
- type
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 230000000903 blocking effect Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005253 cladding Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 abstract description 4
- 240000002329 Inga feuillei Species 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 230000004069 differentiation Effects 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 238000010893 electron trap Methods 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 238000004891 communication Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005524 hole trap Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高速変調可能な高抵抗半導体層埋め込み型二
重ヘテロ構造半導体レーザに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-resistance semiconductor layer-embedded double heterostructure semiconductor laser capable of high-speed modulation.
（従来の技術）
高度情報化社会の構築に伴い、光通信システムの大容量
化、通信ネットワークの高度化が進められている。光通
信システムの大容量化に有力な１つの手段として変調速
度の高速化が上げられる。光源を超高速変調して高速化
を図った光通信システムにおいては、高速応答に優れた
半導体レーザが要求される。(Prior Art) With the construction of an advanced information society, optical communication systems are increasing in capacity and communication networks are becoming more sophisticated. One effective means for increasing the capacity of optical communication systems is increasing the modulation speed. In optical communication systems that aim to increase speed by modulating a light source at ultra-high speed, semiconductor lasers with excellent high-speed response are required.
半導体レーザの活性領域にのみ電流を有効に閉じ込め、
屈折率差により光も活性領域に有効に閉じ込めるための
埋め込み層として、近年、半導体中の深い準位を利用し
た高抵抗半導体層を用いることが注目され盛んに研究・
開発がされている。高抵抗半導体層を埋め込み層に用い
た半導体レーザでは、ｐ−ｎ接合電流ブロック層を活性
領域への電流狭窄に用いられていないため、寄生容量が
小さく高速変調が可能であることが知られている。（ア
プライド・フィジックス・レターズ（ａｐｐｌｉｅｄ
ｐｈｙｓｉｃｓｌｅｔｔｅｒｓ）誌、第４５巻、第４号
、３１１頁）高抵抗半導体層を埋め込み層に用いた半導
体レーザの従来例を第４図に示す。ストライプ状の活性
層４２の両側を電子或るいは正孔を捕獲する深い準位を
有する高抵抗半導体層４４で埋め込み電流を有効に活性
層に注入しようとするものである。Effectively confines current only to the active region of the semiconductor laser,
In recent years, the use of high-resistance semiconductor layers that utilize deep levels in semiconductors has attracted attention and has been actively researched as a buried layer to effectively confine light in the active region due to the difference in refractive index.
It is being developed. It is known that in semiconductor lasers that use a high-resistance semiconductor layer as a buried layer, a p-n junction current blocking layer is not used for current confinement to the active region, so parasitic capacitance is small and high-speed modulation is possible. There is. (Applied Physics Letters)
(Physics Letters), Vol. 45, No. 4, Page 311) A conventional example of a semiconductor laser using a high-resistance semiconductor layer as a buried layer is shown in FIG. The purpose is to effectively inject a buried current into the active layer by using a high resistance semiconductor layer 44 having a deep level that captures electrons or holes on both sides of the striped active layer 42.
４１．４３はｐ形あるいはｎ形クラツド層である。41 and 43 are p-type or n-type cladding layers.
（発明が解決しようとする課題）
上述した従来の技術では、電流ブロック層４４において
電子或るいは正孔のいずれか一方のみを捕獲する半絶縁
性半導体層（ＳＩ）を使うため電流ブロック層４４をｐ
形クラツド層とｎ形クラツド層とではさむ形になり、ｐ
／ＳＩ／ｎ構造が生じる。この部分ではダブルインジエ
クションが発生し活性領域以外を流れる漏れ電流が流れ
る。電流ブロック層が電子を捕獲する半絶縁性半導体層
である場合はｐ層からのホール電流が流れ、正孔を捕獲
する半絶縁性半導体層である場合はｎ層からの電子電流
が流れ、活性領域以外を流れる電流となり、しきい値電
流の上昇、外部微分量子効率の低下、最大出力の低下と
いう半導体レーザの特性の劣化を招いていた。このため
、従来の技術では、高抵抗半導体層を電流ブロック層に
用いた高性能な半導体レーザを得ることが困難であった
。(Problems to be Solved by the Invention) In the conventional technology described above, the current blocking layer 44 uses a semi-insulating semiconductor layer (SI) that captures only either electrons or holes. p
It is sandwiched between a type cladding layer and an n-type cladding layer, and the p
/SI/n structure results. Double injection occurs in this portion, causing leakage current to flow outside the active region. When the current blocking layer is a semi-insulating semiconductor layer that captures electrons, a hole current flows from the p-layer, and when it is a semi-insulating semiconductor layer that captures holes, an electron current flows from the n-layer, resulting in activation. The current flows outside the region, leading to deterioration of semiconductor laser characteristics such as an increase in threshold current, a decrease in external differential quantum efficiency, and a decrease in maximum output. Therefore, with conventional techniques, it has been difficult to obtain a high-performance semiconductor laser using a high-resistance semiconductor layer as a current blocking layer.
本発明の目的は、上記従来技術の欠点を改善し、優れた
半導体レーザを提供することにある。An object of the present invention is to improve the above-mentioned drawbacks of the prior art and provide an excellent semiconductor laser.
（課題を解決するための手段）
本発明における半導体レーザは、半導体基板上にｐ型及
びｎ型のクラッド層及び活性層を有しかつ少なくとも活
性層を含むストライプ状のメサが形成され、このメサ側
面を電子または正孔を捕獲する深い不純物準位を有した
高抵抗半導体層を埋め込むことによって電流ブロック層
とした高抵抗半導体層埋め込み型二重ヘテロ構造半導体
レーザにおいて、前記高抵抗半導体層中で深い不純物準
位を有する不純物のドーピングの割合が変化しているこ
とを特徴とする。(Means for Solving the Problems) In the semiconductor laser of the present invention, a striped mesa having p-type and n-type cladding layers and an active layer and including at least the active layer is formed on a semiconductor substrate. In a high-resistance semiconductor layer-embedded double heterostructure semiconductor laser in which a current blocking layer is formed by embedding a high-resistance semiconductor layer having a deep impurity level that captures electrons or holes on the side surface, in the high-resistance semiconductor layer. It is characterized by a change in the doping ratio of impurities having deep impurity levels.
（作用）
第５図（ａ）は、ｐ型半導体層、深い電子捕獲準位を有
する半絶縁性半導体層、ｎ型半導体層を接触し、順方向
バイアス電圧をかけたときのエネルギーバンドの概念図
である。また、第５図（ｂ）は、ｐ型半導体層、深い正
孔捕獲準位を有する半絶縁性半導体層、ｎ型半導体層を
接触し、順方向バイアス電圧をかけたときのエネルギー
バンドの概念図である。(Function) Figure 5(a) shows the concept of energy bands when a p-type semiconductor layer, a semi-insulating semiconductor layer with a deep electron trapping level, and an n-type semiconductor layer are brought into contact and a forward bias voltage is applied. It is a diagram. Furthermore, Fig. 5(b) shows the concept of the energy band when a p-type semiconductor layer, a semi-insulating semiconductor layer with a deep hole trapping level, and an n-type semiconductor layer are brought into contact and a forward bias voltage is applied. It is a diagram.
従来の高抵抗半導体層埋め込み型半導体レーザでは、ｐ
型クラツド層と高抵抗半導体層とｎ型クラッド層が直接
つながっており、半導体レーザ駆動時には、順方向にバ
イアス電圧がかけられるため、第５図（ａ）ないしは（
ｂ）に示すエネルギーバンドの概念図と等価になる。こ
のため、深い電子捕獲準位を有する半絶縁性半導体層の
場合は、ｐ型クラツド層と半絶縁性半導体層の界面付近
において電子と正孔が再結合し、再結合電流が流れる。In conventional high-resistance semiconductor layer embedded semiconductor lasers, p
The type cladding layer, the high-resistance semiconductor layer, and the n-type cladding layer are directly connected, and a forward bias voltage is applied when the semiconductor laser is driven.
This is equivalent to the conceptual diagram of the energy band shown in b). Therefore, in the case of a semi-insulating semiconductor layer having a deep electron trapping level, electrons and holes recombine near the interface between the p-type cladding layer and the semi-insulating semiconductor layer, and a recombination current flows.
また、深い正孔捕獲準位を有する半絶縁性半導体層の場
合は、ｎ型クラッド層と半絶縁性半導体層の界面付近に
おいて電子と正孔が再結合し、再結合電流が流れる。Further, in the case of a semi-insulating semiconductor layer having a deep hole trapping level, electrons and holes recombine near the interface between the n-type cladding layer and the semi-insulating semiconductor layer, and a recombination current flows.
一方、第６図（ａ）に本発明の電流ブロノク層のエネル
ギーバンドの概念図を示す。図は、深い電子捕獲準位を
有する半絶縁性半導体層の場合で、ｎ型半導体付近の電
子捕獲準位密度を高くすることによりｎ型層から注入さ
れる電子をより多く捕獲し、ｐ型半導体層付近の電子捕
獲準位密度を低くすることによりｐ型半導体層から注入
される正孔と深い準位に捕獲された電子との再結合を抑
制することができる。次に、第６図（ｂ）に本発明の電
流ブロック層のエネルギーバンドの概念図を示す。図は
、深い正孔捕獲準位を有する半絶縁性半導体層の場合で
、ｐ型半導体層付近の正孔捕獲準位密度を高くすること
によりｐ型半導体層から注入される正孔をより多く捕獲
し、ｎ型半導体層付近の正孔捕獲準位密度を低くするこ
とにより、ｎ型半導体層から注入される電子と深い準位
に捕獲された正孔との再結合を抑制することができると
考えられる。On the other hand, FIG. 6(a) shows a conceptual diagram of the energy band of the current Bronnock layer of the present invention. The figure shows the case of a semi-insulating semiconductor layer with a deep electron trapping level. By increasing the density of electron trapping levels near the n-type semiconductor, more electrons injected from the n-type layer can be captured, and the p-type By lowering the density of electron trapping levels near the semiconductor layer, recombination of holes injected from the p-type semiconductor layer and electrons trapped in deep levels can be suppressed. Next, FIG. 6(b) shows a conceptual diagram of the energy band of the current blocking layer of the present invention. The figure shows the case of a semi-insulating semiconductor layer with a deep hole trapping level. By increasing the hole trapping level density near the p-type semiconductor layer, more holes can be injected from the p-type semiconductor layer. By trapping electrons and lowering the hole trapping level density near the n-type semiconductor layer, recombination between electrons injected from the n-type semiconductor layer and holes captured in deep levels can be suppressed. it is conceivable that.
以上述べたように、本発明による高抵抗層埋め込み型半
導体レーザにおいては、漏れ電流が抑制され、活性層に
おいて注入電流が有効に光に変換されるため、低しきい
値電流、高い外部微分量子効率、高い光出力を期待する
ことができる。As described above, in the high-resistance layer embedded semiconductor laser according to the present invention, leakage current is suppressed and the injected current is effectively converted into light in the active layer, resulting in a low threshold current and high external differential quantum. You can expect high efficiency and high light output.
（実施例）
次に本発明について、図面を参照して説明する。第１図
は、本発明の第一実施例の図である。実施例においては
、長波長系材料である燐火インジウム（ＩｎＰ）系材料
の例を説明する。(Example) Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram of a first embodiment of the invention. In the embodiment, an example of an indium phosphorous (InP) material, which is a long wavelength material, will be explained.
まず、（１００）面の出た硫黄（Ｓ）ドーピングｎ型Ｉ
ｎＰ基板１１上に有機金属気相戒長法（ＭＯＶＰＥ）を
用いて、シリコン（Ｓｉ）ドーピングｎ型ＩｎＰ層１８
［ｎ＝ＩＸ１０ ａｍ３］を厚さ１１１ｍ、発光波長１
．５５１１ｍのバンドギャップを有するインジウム・ガ
リウム・ひ素・燐（ＩｎＧａＡｓＰ）活性層１９を厚さ
０．１５１１ｍ、亜鉛（Ｚｎ）ドーピングｐ型ＩｎＰ層
ＩｎＧａＡｓＰコンタクト層１７［ｐ ＝ＩＸ１０ ｃ
ｍ ］を厚さ１．５ｐｍ、それぞれ連続的にエビタキシ
ャル或長する。次にフォトリソグラフィーの手法により
、＜０１１＞方向に厚み約２０００人、幅２ｐｍのＳｉ
０２ストライプ状マスクを３００ｐｍ間隔で形戒する。First, sulfur (S) doped n-type I with (100) plane
A silicon (Si) doped n-type InP layer 18 is formed on the nP substrate 11 using a metal organic vapor phase process (MOVPE).
[n=IX10 am3] with a thickness of 111 m and an emission wavelength of 1
．． An indium gallium arsenide phosphorous (InGaAsP) active layer 19 having a band gap of 5511 m is formed to a thickness of 0.1511 m, and a zinc (Zn) doped p-type InP layer InGaAsP contact layer 17 [p = IX10 c
m] to a thickness of 1.5 pm, respectively, are continuously emitted and elongated. Next, using photolithography, a Si film with a thickness of approximately 2000 layers and a width of 2 pm was fabricated in the <011> direction.
02 striped masks are applied at intervals of 300 pm.
次に、化学エノチングによりｐ型ＩｎＧａＡｓＰコンタ
クト層１７、ｐ型ＩｎＰ層２０，ＩｎＧａＡｓＰ活性層
１９，ｎ型ＩｎＰ層１８をメサストライプの高さが３．
５￥１ｍになるようにエッチングする。さらに、Ｓｉ０
２ストライプ状マスクを残したまま、メサストライプの
凹部分に鉄（Ｆｅ）ドーピング高抵抗ＩｎＰ層１２を厚
さ３．５￥１ｍをＭＯＶＰＥにより全体が平坦になるよ
うに選択エビタキシャル成長する。Next, by chemical etching, the p-type InGaAsP contact layer 17, the p-type InP layer 20, the InGaAsP active layer 19, and the n-type InP layer 18 are formed so that the mesa stripe has a height of 3.
5. Etch to 1m. Furthermore, Si0
With the two-stripe mask remaining, an iron (Fe)-doped high-resistance InP layer 12 is selectively epitaxially grown in the concave portion of the mesa stripe to a thickness of 3.5 yen by MOVPE so that the entire surface is flat.
第１図の右側に、このときのＦｅドーピング高抵抗Ｉｎ
Ｐ層のＦｅドーピング分布を示す。戒長中にドーパント
原料の流量を変化させ、未捕獲トラップ濃度が基板側か
ら表面側に向かってＩ Ｘ １０１５ａｍ’から１×１
０１６ｃｍ−３まで変化するようにする。次に、Ｓｉ０
２ストライプ状マスクを弗酸により除去した後、全体の
厚さが１２０ｐｍ程度になるまで研磨し、ｐ型半導体側
、及びｎ型半導体基板側の電極１０を真空蒸着により形
或し、アニーリングした後、個々の半導体レーザにへき
開分離し、全加工を終了し、第１図に断面を示す半導体
レーザが出来上がる。On the right side of Figure 1, the Fe-doped high-resistance In
The Fe doping distribution of the P layer is shown. By changing the flow rate of the dopant raw material during the pretreatment, the concentration of uncaptured traps increases from I x 1015 am' to 1 x 1 from the substrate side to the surface side.
It is made to vary up to 0.016 cm-3. Next, Si0
After removing the two-stripe mask with hydrofluoric acid, it was polished until the total thickness was about 120 pm, and the electrodes 10 on the p-type semiconductor side and the n-type semiconductor substrate side were formed by vacuum evaporation or annealed. Then, the semiconductor laser is cleaved and separated into individual semiconductor lasers, and all processing is completed to complete the semiconductor laser whose cross section is shown in FIG.
この半導体レーザでは、活性層以外を流れる無効電流が
殆ど無く、ｐ−ｎ接合をブロック層に用いたＶＳＢ型（
Ｖ−ｇｒｏｏｖｅｄ Ｓｕｂｓｔｒａｔｅ Ｂｕｒｉｅ
ｄ ＨｅｔｅｒｏｓｔｒｕｃｔｕｒｅＬａｓｅｒｓ）や
ＤＣ−ＰＢＨ型（Ｄｏｕｂｌｅ Ｃｈａｎｎｅｌ Ｐｌ
ａｎａｒ ＢｕｒｉｅｄＨｅｔｅｒｏｓｔｒｕｃｔｕｒ
ｅ Ｌａｓｅｒｓ）と同程度の１０ｍＡ前後のしきい値
電流、及び３０％前後の片面外部微分量子効率が得られ
る。更に、厚さ２〜３ｐｍの高抵抗半導体層を電流ブロ
ソク層に用いているので、寄生容量は４〜５ｐＦで、数
ギガビット毎秒（Ｇｂ／ｓｅｅ）クラスの光通信システ
ム用光源として実用的に十分使用できる。In this semiconductor laser, there is almost no reactive current flowing through anything other than the active layer, and the VSB type (
V-grooved Substrate Burie
d Heterostructure Lasers) and DC-PBH type (Double Channel Pl
anar BuriedHeterostructure
A threshold current of around 10 mA, which is comparable to that of e Lasers), and a single-sided external differential quantum efficiency of around 30% can be obtained. Furthermore, since a high-resistance semiconductor layer with a thickness of 2 to 3 pm is used for the current blocking layer, the parasitic capacitance is 4 to 5 pF, which is sufficient for practical use as a light source for several gigabits per second (Gb/see) class optical communication systems. Can be used.
次に、第２図は、本発明の第２実施例の図である。まず
、（１００）面の出たＳドーピングｎ型ＩｎＰ基板１１
上にＭＯＶＰＥを用いて、Ｓｉドーピングｎ型ＩｎＰ層
１８［ｎ＝ＩＸ１０ ａｍ ］を厚さｌｐｍ、発光波長
１．５５ｐｍのバンドギャップを有するＩｎＧａＡｓＰ
活性層１９を厚さ０．１５ｌｌｍ， Ｚｎドーピングｐ
型ＩｎＧａＡｓＰコンタクト層１７［ｎ ＝ＩＸ１０
ｃｍ ］を厚さ０．５ｐｍ、それぞれ連続的にエビタキ
シャル戒長ずる。次にフォトリソグラフィーの手法によ
り、＜０１１＞方向に厚み２００ＯＡ，幅２ｐｍのＳｉ
０２ストライプ状マスクを３００ｐｍ間隔で形成する。Next, FIG. 2 is a diagram of a second embodiment of the present invention. First, an S-doped n-type InP substrate 11 with the (100) plane exposed.
Using MOVPE, a Si-doped n-type InP layer 18 [n=IX10 am] was formed using InGaAsP having a thickness of 1 pm and a bandgap of an emission wavelength of 1.55 pm.
The active layer 19 has a thickness of 0.15 llm and is doped with Zn.
Type InGaAsP contact layer 17 [n = IX10
cm ] to a thickness of 0.5 pm, and were continuously ebitaxially lengthened. Next, using photolithography, a Si film with a thickness of 200 OA and a width of 2 pm was fabricated in the <011> direction.
02 stripe-like masks are formed at intervals of 300 pm.
次に、化学エッチングによりｐ型ＩｎＧａＡｓＰコンタ
クト層１７，ｐ型ＩｎＰ層２０，ＩｎＧａＡｓＰ活性層
１９，ｎ型ＩｎＰ層１８をメサストライプの高さが３．
５ｐｍになるようにエッチングする。さらに、Ｓｉ０２
ストライブ状マスクを残したまま、メサストライプの凹
部分にチタン（Ｔｉ）ドーピング高抵抗ＩｎＰ層１５を
厚さ３．５ｐｍをＭＯＶＰＥにより全体が平坦になるよ
うに選択エビタキシャル威長ずる。第２図の右側に、こ
のときＴｉドーピング高抵抗ＩｎＰ層１５のＴｉドーピ
ング分布を示す。成長中にドーパント原量の流量を変化
させ、未捕獲トラップ濃度が基板側から表面側にむかっ
て、ＩＸＩＯ ａｍから１×１０ｃｍまで変化するよう
にする。次に、Ｓｉ０２ストライプ状マスクを弗酸によ
り除去した後、全体の厚さが１２０ｐｍ程度になるまで
研磨し、ｐ型半導体側、及びｎ型半導体基板側の電極１
０を真空状着法により形成し、アニーリングした後、個
々の半導体レーザにへき開分離し、全加工を終了し、第
２図に断面を示す半導体レーザが出来上がる。この半導
体レーザでは、１０ｍＡ前後のしきい値電流、及び３０
％前後の片面外部微分量子効率が得られる。更に、厚さ
２〜３ｐｍの高抵抗半導体層を電流ブロック層に用いて
いるので、寄生容量は、４〜５ｐＦで、数ギガビット毎
秒（Ｇｂ／ｓｅｃ）クラスの光通信システム用光源とし
て実用的に十分使用できる。Next, by chemical etching, the p-type InGaAsP contact layer 17, the p-type InP layer 20, the InGaAsP active layer 19, and the n-type InP layer 18 are formed so that the mesa stripe height is 3.
Etch to a thickness of 5 pm. Furthermore, Si02
While leaving the stripe-like mask, a titanium (Ti)-doped high-resistance InP layer 15 with a thickness of 3.5 pm is selectively epitaxially grown in the concave portion of the mesa stripe by MOVPE so that the entire surface is flat. The right side of FIG. 2 shows the Ti doping distribution of the Ti-doped high-resistance InP layer 15 at this time. The flow rate of the dopant source is varied during growth so that the uncaptured trap concentration varies from the substrate side to the surface side from IXIO am to 1×10 cm. Next, after removing the Si02 striped mask with hydrofluoric acid, it was polished until the total thickness was about 120 pm, and the electrodes 1 on the p-type semiconductor side and the n-type semiconductor substrate side were removed.
0 is formed by a vacuum bonding method, annealed, and then cleaved and separated into individual semiconductor lasers.All processing is completed, and a semiconductor laser whose cross section is shown in FIG. 2 is completed. This semiconductor laser has a threshold current of around 10 mA and a threshold current of around 30 mA.
A single-sided external differential quantum efficiency of around % can be obtained. Furthermore, since a high-resistance semiconductor layer with a thickness of 2 to 3 pm is used as the current blocking layer, the parasitic capacitance is 4 to 5 pF, making it practical as a light source for several gigabit per second (Gb/sec) class optical communication systems. Fully usable.
次に、第３図は、本発明の第３実施例の図である。第１
図、示す実施例に於で、Ｆｅのドーピング分布が第３図
の右側に示すようにｎ型半導体１８に接する部分とｐ型
半導体２０に接する部分で急激に変化している場合であ
る。この半導体レーザは１０ｍＡ前後のしきい値電流、
及び３０％前後の片面外部微分量子効率が得られる。更
に、厚さ２〜３ｌｌｍの高抵抗半導体層を電流ブロック
層に用いてるゆえ、寄生容量は，４〜５ｐＦで、数ギガ
ビット毎秒（Ｇｂ／ｓｅｃ）クラスの光システム用光源
として実用的に十分使用できる。Next, FIG. 3 is a diagram of a third embodiment of the present invention. 1st
In the embodiment shown in FIG. 3, the doping distribution of Fe changes rapidly between the portion in contact with the n-type semiconductor 18 and the portion in contact with the p-type semiconductor 20, as shown on the right side of FIG. This semiconductor laser has a threshold current of around 10mA,
And a single-sided external differential quantum efficiency of around 30% can be obtained. Furthermore, since a high-resistance semiconductor layer with a thickness of 2 to 3 llm is used as the current blocking layer, the parasitic capacitance is 4 to 5 pF, which is sufficient for practical use as a light source for several gigabit per second (Gb/sec) class optical systems. can.
なお、Ｔｉをドーパントする場合はドーピング濃度の変
化の仕方がＦｅの場合と逆になる。Note that when using Ti as a dopant, the way the doping concentration changes is opposite to that when using Fe.
また、基板がｐ型の場合については第１図、第２図、第
３図に示す電流ブロック層のドーピング分布はまったく
逆の形になる。Furthermore, when the substrate is of p-type, the doping distribution of the current blocking layer shown in FIGS. 1, 2, and 3 is completely reversed.
（発明の効果）
以上に説明したように本発明は、電流ブロック層に電子
または正孔を捕獲する深い準位を有した半絶縁性半導体
層を用い、このドーピング分布を変えることにより、高
抵抗半導体埋め込み型半導体レーザの低しきい値電流、
高い外部微分量子効率、超高速変調特性を実現できる効
果がある。(Effects of the Invention) As explained above, the present invention uses a semi-insulating semiconductor layer having a deep level that captures electrons or holes in the current blocking layer, and by changing this doping distribution, high resistance is achieved. Low threshold current of embedded semiconductor laser,
This has the effect of realizing high external differential quantum efficiency and ultra-high speed modulation characteristics.
第１図は、本発明による高抵抗半導体埋め込み型半導体
レーザの第一の実施例を示す図である。第２図は、本発
明による高抵抗半導体層埋め込み型半導体レーザの第二
の実施例を示す図である。第３図は、本発明による高抵
抗半導体埋め込み型半導体レーザの第三の実施例を示す
図である。第４図は、従来の高抵抗電流ブロック層を有
する半導体レーザの構造を示す断面すである。第５図（
ａ）は、ｎ型半導体層、深い電子トラップ準位を有する
半絶縁性半導体層、ｐ型半導体層が接し、これに順バイ
アスがかけられたときのバンド構造を示す概念図である
。第５図（ｂ）は、ｎ型半導体層、深い正孔トラップ順
位を有する半絶縁性半導体層、ｐ型半導体層が接し、こ
れに順バイアスがかけられたときのバンド構造を示す概
念図である。第６図（ａ）は、ｎ型半導体層、深い電子
トラップ準位を有する半絶縁性半導体層、ｐ型半導体層
が接したときのバンド構造を示す概念図である。但し、
ｎ型半導体付近のドーピングを多くし、ｐ型半導体付近
のドーピングを少なくしている。第６図（ｂ）は、ｎ型
半導体層、深い正孔トラップ準位を有する半絶縁性半導
体層、ｐ型半導体層が接したときのバンド構造を示す概
念図である。但し、ｎ型半導体付近のドーピングを少な
くし、Ｐ型半導体付近のドーピングを多くしている。
１０；電極、１１；ｎ型ＩｎＰ基板、１２；Ｆｅドーピ
ング高抵抗ＩｎＰ層、１５；Ｔｉドーピング高抵抗Ｉｎ
Ｐ層、１７；ｐ型ＩｎＧａＡｓＰコンタクト層、１８；
ｎ型ＩｎＰ層、１９；ＩｎＧａＡｓＰ活性層、２０；ｐ
型ＩｎＰ層、４０；半導体基板、４１；第１のクラッド
層、４２；活性層、４３：第２のクラツド層、４４；高
抵抗半導体層、４５；コンタクト層、４６；絶縁膜、４
７；電極、４８；電極。FIG. 1 is a diagram showing a first embodiment of a high-resistance embedded semiconductor laser according to the present invention. FIG. 2 is a diagram showing a second embodiment of the high-resistance semiconductor layer-embedded semiconductor laser according to the present invention. FIG. 3 is a diagram showing a third embodiment of a high-resistance embedded semiconductor laser according to the present invention. FIG. 4 is a cross-sectional view showing the structure of a conventional semiconductor laser having a high resistance current blocking layer. Figure 5 (
a) is a conceptual diagram showing a band structure when a forward bias is applied to an n-type semiconductor layer, a semi-insulating semiconductor layer having a deep electron trap level, and a p-type semiconductor layer in contact with each other; Figure 5(b) is a conceptual diagram showing the band structure when a forward bias is applied to an n-type semiconductor layer, a semi-insulating semiconductor layer with a deep hole trap level, and a p-type semiconductor layer in contact with each other. be. FIG. 6(a) is a conceptual diagram showing a band structure when an n-type semiconductor layer, a semi-insulating semiconductor layer having a deep electron trap level, and a p-type semiconductor layer are in contact with each other. however,
Doping in the vicinity of the n-type semiconductor is increased, and doping in the vicinity of the p-type semiconductor is decreased. FIG. 6(b) is a conceptual diagram showing a band structure when an n-type semiconductor layer, a semi-insulating semiconductor layer having a deep hole trap level, and a p-type semiconductor layer are in contact with each other. However, the doping in the vicinity of the n-type semiconductor is reduced, and the doping in the vicinity of the p-type semiconductor is increased. 10; electrode, 11; n-type InP substrate, 12; Fe-doped high-resistance InP layer, 15; Ti-doped high-resistance In
P layer, 17; p-type InGaAsP contact layer, 18;
n-type InP layer, 19; InGaAsP active layer, 20; p
type InP layer, 40; semiconductor substrate, 41; first cladding layer, 42; active layer, 43: second cladding layer, 44; high resistance semiconductor layer, 45; contact layer, 46; insulating film, 4
7; electrode; 48; electrode.
Claims (1)
有し、かつ少なくとも活性層を含むストライプ状のメサ
が形成され、このメサ側面を電子または正孔を捕獲する
深い不純物準位を有した高抵抗半導体層を埋め込むこと
によって電流ブロック層とした高抵抗半導体層埋め込み
型二重ヘテロ構造半導体レーザにおいて、前記高抵抗半
導体層中で深い不純物準位を有する不純物のドーピング
の割合が変化していることを特徴とする高抵抗半導体層
埋め込み型半導体レーザ。A striped mesa having p-type and n-type cladding layers and an active layer and including at least the active layer is formed on a semiconductor substrate, and the mesa side surface has a deep impurity level that captures electrons or holes. In the high-resistance semiconductor layer-embedded double heterostructure semiconductor laser which uses a high-resistance semiconductor layer as a current blocking layer by embedding a high-resistance semiconductor layer, the doping ratio of an impurity having a deep impurity level in the high-resistance semiconductor layer changes. A high-resistance semiconductor layer-embedded semiconductor laser characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1139522A JP2780337B2 (en) | 1989-05-31 | 1989-05-31 | High-resistance semiconductor layer embedded semiconductor laser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1139522A JP2780337B2 (en) | 1989-05-31 | 1989-05-31 | High-resistance semiconductor layer embedded semiconductor laser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0354882A true JPH0354882A (en) | 1991-03-08 |
| JP2780337B2 JP2780337B2 (en) | 1998-07-30 |
Family
ID=15247250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1139522A Expired - Fee Related JP2780337B2 (en) | 1989-05-31 | 1989-05-31 | High-resistance semiconductor layer embedded semiconductor laser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780337B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003060309A (en) * | 2001-08-21 | 2003-02-28 | Sumitomo Electric Ind Ltd | Semiconductor laser |
| EP1233445A3 (en) * | 2001-02-15 | 2006-06-07 | Eudyna Devices Inc. | Process of manufacturing a semiconductor device |
| CN109546531A (en) * | 2017-09-22 | 2019-03-29 | 株式会社沙迪克 | The manufacturing method of luminescent device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477979A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Embedded type semiconductor laser device |
-
1989
- 1989-05-31 JP JP1139522A patent/JP2780337B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477979A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Embedded type semiconductor laser device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1233445A3 (en) * | 2001-02-15 | 2006-06-07 | Eudyna Devices Inc. | Process of manufacturing a semiconductor device |
| US7303933B2 (en) | 2001-02-15 | 2007-12-04 | Fujitsu Quantum Devices Limited | Process of manufacturing a semiconductor device |
| US7919415B2 (en) | 2001-02-15 | 2011-04-05 | Fujitsu Quantum Devices Limited | Process of manufacturing a semiconductor device |
| JP2003060309A (en) * | 2001-08-21 | 2003-02-28 | Sumitomo Electric Ind Ltd | Semiconductor laser |
| CN109546531A (en) * | 2017-09-22 | 2019-03-29 | 株式会社沙迪克 | The manufacturing method of luminescent device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2780337B2 (en) | 1998-07-30 |
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