JPH0354939A - Method of controlling interface - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Required) Regarding the interface-based tlDt method for multiple devices to operate in synchronization with each other, the purpose of this invention is to simplify the so-note processing and to correctly control the time relationship. Multiple devices are connected to a common bus through input/output devices,
In the interface control method of the system, the input/output device is configured to operate in synchronization with the common bus. determining means for determining which of the output completion notification inputted each time the output is completed and the input notification of received data inputted via the common bus is inputted first; and reading means for reading the data input earlier based on the data input.

[Industrial Application Field] The present invention relates to an interface tI11wJ method, and particularly to an interface It. Regarding the lJI11 method.

In recent years, various proposals have been made to systemize various information devices using home information communication channels (home buses). In this home bus, information outlets are installed in the home bus wired to each room, and telephones, television receivers, intercoms, etc.
By connecting personal computers, security system equipment, and other devices to this information outlet, users can receive designated services, and the idea is to closely connect home life with various outdoor social functions through information communication.

In a system such as a home bus, multiple devices are connected to a common bus and operate in synchronization with each other, so the input/output interface of multiple devices is
lltll is important.

[Conventional technology]

In a system having a plurality of devices 1 to 5 as shown in FIG. 4, devices 1, 2 and 3 each have individual input/output devices! ! (
Via the I/O devices 6.7 and 8, the VI devices 4 and 5 are each commonly connected to the bus 10 via a common 1/0 device 9. These 8l units 1 to 5 are I/O devices 6
.about.9 to the bus 10, and transmit and receive data so that they operate in the same way.

Therefore, if one of the devices 1 to 5 is making its first production, all other devices will know about it.
This allows the bus 10 to be occupied and data to be transferred to other devices without any hindrance.

However, there is no problem if devices 1 to 3 are equipped with dedicated I/O devices 6 to 8, but devices 4 and 5 are equipped with dedicated I/O devices 6 to 8.
When two devices share one I/O device 9 (for example, a home bus controller and a telephone, which have one casing but two functions (devices)), the cost In order to reduce the number of I/O units, there is often only one I/O unit U.If data is sent and received only between units 4 and 5, the operation information will be transmitted to other units. The f1 system is no longer synchronized.

Conventionally, when data is transferred from one of the devices 4 and 5 to the other, as shown in FIG. Based on this, the above data is also output serially to the bus 10 via the input/output device 9.

(5! Problems to be Solved by the Invention) However, while there is a time delay in the actual serial data transfer via the bus 10 between the I/O devices 6 to 9, Since the data transfer between is performed in parallel, there is no time delay, and therefore devices 4 and 5 can output the next data before the other TA devices receive the data normally. This will break the overall synchronization.

Therefore, in the past, processing such as placing a wait was performed using the I/O interface software S shown in Fig. 5, but this Sonoto I? I/O devices 6 to 9 depending on processing
In order to accurately match the actual serial data transfer delay time of 1F18, the software becomes complicated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an interface control method that can simplify software processing and correctly control time relationships.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, reference numeral 11 denotes an input/output unit provided corresponding to the equipment, and a common bus 1.
Multiple connections are made via 2.

Reference numeral 13 denotes a determining means that determines which of the output end notification inputted every time transmission data is outputted to the common bus 12 and the reception data input notification inputted via the common bus 12 is inputted first. do.

Reference numeral 14 denotes a reading means, which reads the data input earlier based on the output of the determining means 13.

[Inquiry]

The determination means 13 determines whether the transmission data is being transmitted each time the transmission data is output to the common bus 12. Therefore, when the transmission data is serially transferred to the common bus 12, the time when the last bit of one data is transferred is determined. to determine data transmission.

Since the reading stage 14 reads the transmitted data based on this data transmission determination output, the input/output unit 11 is commonly connected to a plurality of devices. ! 2r! Even if data is transferred in parallel between 1 devices, the hardware configuration allows other devices to read the transmitted data at the same time as they receive it.

(Example〕 FIG. 2 shows a block diagram of an embodiment of the main part of the present invention.

This embodiment is an embodiment corresponding to the discrimination f stage 13, and the transmission data from the device (not shown) is sent to the transmission vane 716.
After the time is stored, it is input to the shift register or handshake circuit 17. 18 and is temporarily stored.

Here, when serial data transmission is performed between multiple devices via a bus, a start bit is added to the beginning of the data bit of Do"Dt+, and , a validity bit Dp and a stop bit are added after the data bit, forming a data format that constitutes a 1# character.

While the shift register or handshake circuit 17 sends the input transmission data to the bus, it determines that the transmission data has been output onto the bus and has finished by detecting the stop bit in FIG. 3, and sends the completion notification signal. It is supplied to the status register 19.

On the other hand, data sent from other VI devices via the bus is input to the shift register or handshake circuit 20, where it is received and then stored in the receive buffer. 21.

Is status register 19 a transmission buffer? 16, a transmission completion notification signal for each data from the shift register or handshake circuit 17, and a reception buffer? The received data input information from the central processing unit t? t
(CPLJ) or the like to the reading means 14.

The CPU constituting the reading stage 14 reads the status of the officer, as well as the transmission data from the buffer 718 and the reception buffer 7.
Among the received data from 21, the data that was input first is read.

In this way, according to this embodiment, the data sent by this I/O device can be received and taken in by the sending I/O device itself, so that this I/O device can be transmitted between multiple devices. It is possible to identify time delays in actual transmitted data even when commonly used. Moreover, in this embodiment, since the time delay can be identified by hardware processing rather than software processing, the software processing can be simplified compared to the conventional method.

Note that the present invention is not limited to the above-described embodiment, and the buffer 718 may not be provided, and data formats other than those shown in FIG. 3 are also possible.

〔Effect of the invention〕

As described above, according to the present invention, even if the input/output device 4 is commonly connected to a plurality of devices, the input/output device 4 itself receives the data actually transmitted.
It is possible to accurately maintain the same time relationship as when another device connected to the bus receives the transmitted data, and because the hardware configuration maintains r1liS11Il, it requires less software than before. This method has features such as being able to simplify processing.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a block diagram of an embodiment of the main part of the present invention, Fig. 3 is a diagram showing an example of the format of transmission data, and Fig. 4 is a diagram to which the present invention is applied. W4 diagram of the system to be used, No. 5
The figure is an explanatory diagram of the conventional h-type. In the figure, 1 to 5 are devices, 6 to 9 are input/output devices (■/0 equipment), 11 is an input/output device, 12 is a common bus, 13 is a discrimination means, 14 is a reading means, 16 is a transmission buffer 7, 19 indicates a status register. Fig. 1 is a schematic diagram of an embodiment of the main part of the present invention Fig. 2 is an example of the form of transmission data Fig. 3 is a diagram of the structure of the stem in which the present invention is properly carried out Fig. 4 Figure 5 is an explanatory diagram of the conventional method.

Claims (1)

[Claims] A plurality of devices connect to a common bus (1) via an input/output device (11).
2), in which the input/output device (11) is connected to a correspondingly provided device via the input/output device (11). Which of the output completion notification inputted every time the transmission data to be transmitted is finished being output to the common bus (12) and the input notification of reception data inputted via the common bus (12) is input first? a reading means (14) for reading the data input earlier based on the output of the determining means (13);
), an interface control method comprising: