JPH0355046B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generation circuit constructed using insulated gate transistors.

[Conventional technology]

2. Description of the Related Art Conventionally, there has been a circuit shown in FIG. 3, which generates a pulse signal output when an input signal is inverted and is constructed of N-channel transistors.

In the figure, 1 is a high potential point, 2 is a ground point which is a low potential point, 21 to 25 are depletion type transistors, and 26 to 33 are enhancement type transistors.

Depletion mode transistors 21-23 and enhancement mode transistors 26-28
constitutes a three-stage inverter 41 which takes signal a as an input signal and signal b as an output signal, and depletion type transistor 24 and enhancement type transistors 29 and 30 take signal b and signal a as input signals and output signal c, respectively. NOR as a signal
The circuit 42 includes a depletion type transistor 25 and an enhancement type transistor 3.
1 to 33 form a logic circuit 43 which performs NAND with signals a and b, then performs NOR with signal c, and outputs the resulting signal d.

The operation of the conventional pulse generating circuit configured as described above will be explained using the timing chart shown in FIG. Note that FIG. 4A, B, C, and D correspond to signals a to d, respectively.

Now, when a signal a is inputted to the enhancement type transistor 26 as shown in FIG. 4A, a signal b as shown in FIG. 4B is obtained as the final stage output of the inverter 41. That is, signal b is an inverted signal of signal a, and at the same time is a signal with a slight delay. This pulse generation circuit utilizes this delay.

Next, signals a and b are applied to the gates of transistors 29 and 30 as drivers of the NOR circuit 42, respectively.

When signal a is inverted from “L” to “H”,
Since the signal b is delayed and inverted from "H" to "L", one of the drivers 29 and 30 is always in the on state, and the signal c, which is the output signal of the NOR circuit 42, is in the "L" state. It is maintained.

On the other hand, when signal a is inverted from "H" to "L", signal b is delayed and inverted from "L" to "H", so both signals a and b become "L" for the delay time, Drivers 29 and 30 are turned off. Therefore, during this time, the signal c becomes "H", but when the signal b becomes "H", the driver 29 is turned on, so that the signal c returns to "L".

That is, in signal c, a pulse signal can be obtained when signal a is inverted from "H" to "L" (FIG. 4C).

Next, in the logic circuit 43, when the input signal a is inverted from "L" to "H", the signal b is delayed and changes from "H" to "L", so the transistor 3
Since the gates 2 and 33 both become "H" and turn on, the input signal d of the logic circuit 43 becomes "L". After the signal b becomes "L" as the delay time elapses, the transistor 32 is turned off and the signal d returns to "H". That is, the signal d includes a pulse signal "L" generated when the signal a is inverted from "L" to "H".

When the input signal a is inverted from "H" to "L", one of the signals a and b is always "L", so one of the transistors 32 and 33 is always in the off state. However, at this time, since the signal c is input to the gate of the transistor 31, the transistor 31 is turned on by the pulse signal in the signal c, and the signal d is a pulse signal having the same pulse width as the pulse signal in the signal c. Contains “L”.

Eventually, the signal d becomes the signal a, as shown in FIG. 4D.
A pulse will be generated each time the is reversed.

In this way, this conventional circuit can generate a pulse signal output when the input signal is inverted, and since the pulse width of the output signal d is determined by the delay time generated by the inverter 41, it is possible to generate a pulse signal output when the input signal is inverted. It has the advantage that the pulse width can be controlled by arranging an odd number of inverters.

[Problem that the invention seeks to solve]

However, since the above-mentioned conventional circuit is composed of a large number of transistors, the power consumption of the circuit is large, and when the pattern is arranged, the pattern area becomes large.

The present invention has been made in view of the above problems, and its purpose is to reduce the number of transistors, reduce power consumption, and reduce pattern area without losing the advantage of ease of pulse width control. The object of the present invention is to provide a small pulse generation circuit.

[Means for solving problems]

In order to achieve such an object, the present invention provides a NAND circuit composed of insulated gate transistors,
The NAND circuit is provided with transistor circuits respectively connected to the two input terminals of the NAND circuit, and each of the two transistor circuits is constructed by parallel bodies of an enhancement type transistor and a depletion type transistor.

[Effect]

When the input signal to the transistor circuit is inverted from "H" to "L", the input level of the NAND circuit gradually decreases due to the discharge that occurs through the depletion type transistor of the transistor circuit, and conversely, the input signal to the transistor circuit decreases. When the voltage is reversed from "L" to "H", the level of the NAND circuit quickly rises due to the charging performed through the enhancement type transistor of the transistor circuit, so mutually opposing signals are input to the two transistor circuits. Then,
Only when this input signal is inverted, 2 of the NAND circuit
All the signals to the two input terminals become "H", and a pulse signal can be obtained.

〔Example〕

Hereinafter, the present invention will be explained in detail together with examples.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In the figure, 1 is a high potential point, 2 is a ground point which is a low potential point, 3 to 5 are N-channel depletion type transistors, and 6 to 9 are N-channel enhancement type transistors.

The first transistor circuit 11 is the transistor 3
and 6, the drain and gate of transistor 3 and the drain and gate of transistor 6 are all connected in common to serve as an input terminal for signal a, and transistor 3 and source 6 are commonly connected to serve as an output terminal for signal e. do.

The second transistor circuit 12 is the transistor 4
and 7, the drain and gate of transistor 4 and the drain and gate of transistor 7 are all connected in common to serve as an input terminal for a signal that is an inverted signal of signal a, and the sources of transistors 4 and 7 are connected in common. Use this as the signal output terminal.

The NAND circuit 13 is composed of transistors 5, 8, and 9, the drain of the transistor 5 is connected to the high potential point 1, the gate and source thereof are connected in common to the drain of the transistor 8, and the source of the transistor 8 is connected to the high potential point 1. is connected to the drain of transistor 9, and the source of transistor 9 is grounded. The gates of transistors 8 and 9 serve as input terminals, and output terminals of transistor circuits 11 and 12 are connected to them, respectively. Further, the source of the transistor 5 becomes an output terminal and outputs a signal f.

Next, the operation of the embodiment configured as described above will be explained using the timing chart shown in FIG.
Note that A, B, C, D, and E in FIG. 2 correspond to signals a, e, and f, respectively, and broken lines A and B in C and D in the same figure indicate the threshold values of transistors 8 and 9, respectively. .

Signals a, which are input signals to the transistor circuits 11 and 12, are mutually contradictory signals as shown in FIGS. 2A and 2B.

Now, in the transistor circuit 11, the signal a
When is inverted from "L" to "H", the gate voltages of transistors 3 and 6 become "H", and enhancement mode transistor 6 is always turned on. Therefore, if the on-resistance of transistor 6 is made small, the gate of transistor 8, which is one driver on the input side of NAND circuit 13, will be quickly charged through transistor 6, and this gate voltage (signal e) will be The signal becomes "H" and the transistor 8 is turned on.

On the other hand, when the signal a is inverted from "L" to "H", the signal that is the input signal of the transistor circuit 12 is inverted from "H" to "L", and the gate voltages of transistors 4 and 7 both become "L". , the enhancement mode transistor 7 is turned off.

Therefore, the gate of the transistor 9, which is the other driver on the input side of the NAND circuit 13, is discharged through the depletion type transistor 4;
By increasing the resistance value, the gate of the transistor 9 is gradually discharged, and when the gate voltage (signal) of the transistor 9 becomes equal to or lower than the threshold value B, the transistor 9 is turned off.

As can be seen from the above explanation, when the signal a is inverted from "L" to "H", both transistors 8 and 9 are turned on at the moment of inversion.
The output signal f of the NAND circuit 13 becomes "L".
After that, the gate voltage (signal) of transistor 9
gradually decreases, and when it falls below the threshold voltage B, the transistor 9 turns off.
The output signal f of the NAND circuit 13 returns to "H",
A pulse signal is obtained (Fig. 2E).

Conversely, a similar pulse signal can be generated when the signal a is inverted from "H" to "L".

That is, at the moment when the signal a is inverted, both transistors 8 and 9 are turned on, as in the case described above, so the output signal f of the NAND circuit 13 becomes "L", and after that, until the signal a is inverted. Since the signal e holds “H”, the transistor 9
continues to be in the on state, but the signal e is generated through the depletion type transistor 3 and its level decreases due to discharge, and when it falls below the threshold voltage A, the transistor 8 becomes in the off state. Therefore, the output signal f of the NAND circuit 13 returns to "H" and a pulse signal is obtained (FIG. 2E).

Note that the pulse width is determined by the discharge time of the signal e, so if you want to make the pulse width longer, either increase the resistance value of the depletion type transistors 3 and 4, or
It is sufficient to add a capacitor between the gate of No. 9 and the ground.

Further, in the above embodiment, a pulse generation circuit made up of N-channel transistors has been described, but a circuit made up of P-channel transistors or a circuit made up of complementary transistors may be used.

〔Effect of the invention〕

As explained above, the pulse generating circuit of the present invention includes a NAND circuit configured of insulated gate transistors and a transistor circuit connected to each of the two input terminals of the NAND circuit. Since each of the two transistor circuits is constituted by a parallel combination of an enhancement type transistor and a depletion type transistor, the number of transistors can be reduced. Therefore, power consumption can be reduced, and the pattern area when arranging patterns can be reduced, making it very suitable for high integration.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a timing chart showing its operation, FIG. 3 is a circuit diagram showing a conventional pulse generating circuit, and FIG. 4 is a timing chart showing its operation. 3-5...Depression type transistor, 6
~9...Enhancement type transistor, 1
1, 12...transistor circuit, 13...
NAND circuit.

Claims (1)

[Claims] 1. The drain and gate of the depletion mode transistor and the drain and gate of the enhancement mode transistor are all connected in common to serve as an input terminal, and the source of the depletion mode transistor and the source of the enhancement mode transistor are commonly connected to serve as an output terminal. It is composed of two sets of transistor circuits and an insulated gate transistor, and has at least two input terminals.
A pulse generating circuit comprising: a NAND circuit, wherein output terminals of the two sets of transistor circuits are respectively connected to different input terminals of the NAND circuit.