JPH0355908B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program loading method, and more particularly, to a program loading method for loading a program that instructs a series of operations so that a plurality of songs are played in a predetermined playing order into a storage device in an automatic performance player or the like. This invention relates to a method for loading a program to be stored.

Each command in a program that instructs a series of operations of an automatic performance player, etc. is formed by, for example, data specifying each of a plurality of songs to be played, and a numerical value indicating the recording order of the songs recorded on a recording medium such as a record. , serves as a performance instruction for the specified song. FIG. 1 shows a program loading device for storing a program formed by a plurality of such instructions in a storage device using a conventional program loading method. In Figure 1, SW ₀ , SW ₁ ,...
SW ₉ is a numerical input key switch for generating data corresponding to each decimal number from 0 to 9. Each of the key switches _SW0 to _SW9 has one end grounded and the other end connected to each of the corresponding input terminals of the encoder 11. Selectively pressing one of the keyswitches SW ₀ -SW ₉ provides a low level signal to the corresponding input terminal of the encoder 11. Then, the encoder 11 outputs 4-bit BCD (binary coded decimal) coded data corresponding to each decimal number from 0 to 9 and a key input detection signal a consisting of, for example, a high level signal. The 4-bit data output from the encoder 11 is supplied to the register 12. Further, the key input detection signal a output from the encoder 11 is supplied to the write control circuit 13. A write command input terminal of the write control circuit 13 is connected to a write command switch SW ₁₁ whose one end is grounded and the other end thereof. By pressing the write command switch _SW11 , an input data write command signal b consisting of a low level signal is supplied to the write command input terminal. Further, this write control circuit 13 is supplied with a predetermined data write command signal c from a memory clear control circuit 14 . When the write control circuit 13 is supplied with the key input detection signal a, the write control circuit 13 generates a clock pulse d.
is supplied to the register 2, and when the input data write command signal b is supplied, the output buffer control signal e is supplied to the register 12 for a predetermined period of time, and the write address generation command signal f is supplied to the address generation circuit 15. Predetermined data write command signal c
When supplied, a write address generation command signal f is supplied to the address generation circuit 15. Further, the register 12 has a configuration in which two stages of 4-bit parallel registers are connected, for example, and receives a clock pulse d supplied from the write control circuit 13.
The data supplied from the encoder 11 is latched in the register of the previous stage, and the data held in the register of the previous stage is latched in the register of the latter stage. Therefore, by selectively pressing the key switches SW ₁ to SW ₉ twice, two decimal digits of data are held in the register 12.

Next, when the write command switch SW ₁₁ is pressed, the write control circuit 13 supplies the output buffer control signal e to the register 12 and the write address generation command signal f to the address generation circuit 15. The address generation circuit 15 includes, for example, a 4-bit binary counter that counts up in response to the write address generation command signal f and the read address generation command signal g, and a monostable multivibrator that is triggered by the read address generation command signal g. It has a structure that includes The output of the binary counter in the address generation circuit 15 is supplied to the address input terminal of the memory 16. Also, the output buffer control signal is output to the register 12.
, the output buffer in register 12 is activated, and the 8-bit data, in which the lower 4 bits are formed by the output of the previous register and the upper 4 bits are formed by the output of the subsequent register, is converted into BCD code. The resulting two-digit decimal number data is sent to the data bus 17 via the output buffer. Then, the two-digit decimal number data sent to the data bus 17 is stored in a storage location in the memory 16 designated by the output of the address generation circuit 15 as a command for instructing the operation of the automatic performance player.

By repeating the operation of selectively pressing key switches SW ₀ to SW ₉ twice in succession and then pressing switch SW ₁₁ a predetermined number of times, a series of automatic performances are performed according to a predetermined performance order. A program that instructs the operation of is stored in memory 16. Here, if you want to erase the stored contents of the memory 16, such as when an incorrect program is stored due to an erroneous operation of the key switches SW ₀ to SW ₉ , press the clear switch SW ₁₂ , one end of which is grounded, and the switch SW ₁₂ A clear command signal h consisting of a low level signal is supplied to the memory clear control circuit 14 from the other end. Memory clear control circuit 14
supplies a predetermined data write command signal c to the write control circuit 13 a predetermined number of times at predetermined time intervals when the clear command signal h is supplied, and also outputs a two-digit data
It is configured to send 8-bit BCD-coded data to the data bus 17 corresponding to the decimal number "00". For this reason, the clear switch
Address generation circuit 15 is activated by pressing SW ₁₂ .
As the counter counts up, the address specifying the storage location in the memory 16 where the program is to be stored changes sequentially, data "00" is sequentially written to the location where the program was stored, and the storage contents of the memory 16 change. will be deleted.

For example, when an automatic performance start switch (not shown) is pressed after the program is stored without error in the memory 16, a read command signal is supplied to the read control circuit 18 from the control circuit (not shown) of the automatic performance player. Ru. Then, the read address generation command signal g is supplied from the read control circuit 18 to the address generation circuit 15. In the address generation circuit 15, the read address generation command signal g causes a binary counter to count up and a monostable multivibrator to be triggered, so that, for example, a high level signal i with a predetermined time width is output from the Q output terminal of this monostable multivibrator. The signal is output and supplied to the read/write control input terminal of the memory 16 and the clock input terminal of the output buffer circuit 19. Then, the memory 16 is in the read mode for a predetermined period of time, and the address generation circuit 15
The instruction stored in the location specified by the address output of is read out and sent to the data bus 17. This read command is held in the output buffer circuit 19 when, for example, the high level signal i of a predetermined time width outputted from the address generation circuit 15 disappears. The commands held in the output buffer circuit 19 are then supplied to a control circuit (not shown) of the automatic performance player.

As described above, in the device using the conventional program loading method, the clear switch SW ₁₂ is required to erase the stored contents of the memory 16, so the number of operation switches increases, and there are design constraints when miniaturizing the device. As the number of times increases, the operation switch is more likely to be operated erroneously, and in the worst case, the contents of the memory 16 may be erased by mistake.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a program loading method that does not require an operation switch for erasing the contents of a storage device and can prevent the contents of the storage device from being erased erroneously.

The program loading method according to the present invention includes:
It is characterized in that the input data and predetermined data are compared and the stored contents of the storage device are erased only when the input data and the predetermined data match.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

As shown in FIG. 2, key switches _SW0 to _SW9 , write command switch _SW11 , echoer 11, register 12, write control circuit 13, address generation circuit 15, memory 16, data bus 17, read control circuit 18, output buffer circuit 19 are connected in the same way as in FIG. However, in this example, a predetermined data generation circuit 20 is provided which outputs 8-bit BCD coded predetermined data. The output of this predetermined data generation circuit 20 is supplied to a data comparison circuit 21. The data comparison circuit 21 sends a predetermined data write command signal c to the write control circuit 3 at a predetermined time interval when the bit pattern of the output of the register 12 and the bit pattern of the output of the predetermined data generation circuit 20 match. At the same time, the 8-bit BCD coded data corresponding to the 2-digit decimal number "00" is sent to the data bus 17, and when the two bit patterns do not match, the output of the register 12 is sent to the data bus 17. configured to send.

In the above configuration, the predetermined data generation circuit 20
If the data output from the automatic performance player is data that cannot be a command in a program that instructs a series of operations of the automatic performance player, for example, data that corresponds to the decimal number "00", the system can be used similarly to the device shown in Fig. 1. Alternative press of key switch SW ₀ ~ SW ₉ 2
A program for instructing a series of operations is stored in the memory 16 by repeating the operation of pressing the switch SW ₁₁ a predetermined number of times. Also, the same data as the data output from the predetermined data generation circuit 20 is sent to the register 12.
Press the key switches SW ₀ to SW ₉ twice in succession so that the switch is held at
When SW ₁₁ is pressed, the data compared in the data comparison circuit 21 match and the data comparison circuit 2
1, a predetermined data write command signal c is supplied to the write control circuit 13 a predetermined number of times at a predetermined time interval, and an 8-bit data write command signal c corresponding to a two-digit decimal number "00" is supplied.
BCD encoded data is sent to data bus 17. Then, in the same way as when the clear switch SW ₁₂ is pressed in the device shown in FIG. 1, the counter in the address generation circuit 15 counts up and the addresses specifying the storage location in the memory 16 where the program is to be stored sequentially change. Data "00" is sequentially written into the memory location where the program was stored, and the stored contents of the memory 16 are erased. Further, when a read command signal is supplied to the read control circuit 18 from the control circuit (not shown) of the automatic performance player, the command stored in the memory 16 is read out and sent to the output buffer circuit, similar to the device shown in FIG. It is held at 19. The commands held in the output buffer circuit 19 are sent to a control circuit (not shown) of the automatic performance player.

In the above operation, the memory contents of the memory 16 are erased using the numerical input key switches SW ₀ to _{SW 9} and the write command switch in the same way as when each instruction forming the program is stored in the memory 16.
This is when the data sent from the register 12 to the data comparison circuit 21 by operating SW ₁₁ matches the predetermined data, so there is no need for an operation switch such as a clear switch for erasing the memory contents. Since it is possible to reduce the number of devices, it is possible to expect the effects of easier miniaturization of the device and a reduction in erroneous operations. Furthermore, since the stored contents of the memory 16 are erased only when a plurality of operation switches are operated in a predetermined procedure, it is possible to expect the effect that erroneous erasure of the stored contents due to erroneous operations can be prevented.

FIG. 3 is a block diagram showing an example in which a microcomputer is used to configure a device for storing a program for instructing an automatic performance player to perform a series of operations in a storage device using the program loading method according to the present invention. In FIG. 3, a timing pulse generating circuit 30 supplies each input signal line of a key matrix 31 with timing pulses having different generation times. Output signal lines that intersect with the input signal lines are connected to input terminals of the operation switch detection circuit 32. A key switch is installed at each intersection of the input signal line and the output signal line so that the two signal lines are connected when pressed.
SW ₀ to SW ₉ and a write command switch SW ₁₁ are provided. When any one of the switches SW ₀ to SW ₉ and SW ₁₁ is pressed, one of the timing pulses having different generation times is supplied to one of the input terminals of the operation switch detection circuit 32. . Then, the operation switch detection circuit 31 identifies the operation switch that has been pressed and displays the 4-bit information corresponding to the operation switch.
BCD encoded data is output. This 4-bit data is supplied to input port 33 and latched. A read command signal is also supplied to the input port 33 from a control circuit (not shown) of the automatic performance player. From this input port 32, information indicating whether 4-bit data has been latched, information indicating which of the numerical input key switch or write command switch has been pressed, and information indicating whether a read command signal has been supplied. 8-bit data, including the 4-bit data latched with the information, is taken into the processor 35 via the data bus 34. The processor 35 is ROM36, RAM
37 to process the captured data. Then, the processor 35 uses a predetermined area of the RAM 37 as a program memory area to store therein a program that instructs a series of operations of the automatic performance player, erases the stored contents of the program memory area,
Alternatively, the commands stored in the program memory area are read out and sent through the output port 38 to a control circuit (not shown) of the automatic performance player. still,
The address output of the processor 35 is the address bus 3.
Input port 33, ROM36, RAM via 9
37 and output port 38, respectively.

A portion of the operation of the apparatus according to the invention shown in FIG. 3 will now be described with reference to the flowchart shown in FIG. Performs switch input processing operations including determining whether or not the operation switch has been pressed (see Figure 3, S).
1). It is determined whether the pressed operation switch is a numerical input switch (S2 in the figure). When the numerical input switch is pressed, the 4-bit binary coded data contained in the data taken in from the input port 33 is transferred to the RAM 37.
The 4-bit data that has already been written to a buffer having a storage capacity of 8 bits set in a predetermined location other than the program memory area is written so as not to be erased (S3 in the figure), and the process returns to S1. If the pressed switch is not a numerical input switch, it is determined whether the write command switch has been pressed (S4 in the figure), and if the write command switch has not been pressed, the process returns to S1.
If the pressed switch is a write command switch, it is determined whether data corresponding to the two-digit decimal number "00" is written in the buffer (S5 in the same figure). If data corresponding to "00" has been written in the buffer, the contents stored in the program memory area of the RAM 37 are erased (S6 in the figure), and the process returns to S1. If data corresponding to “00” has not been written to the buffer, the RAM
The data written in the buffer is written into the program memory area at 37 as an instruction (S7 in the same figure). Thereafter, 1 is added to the address value for specifying the storage location within the program memory area (S8 in the figure), and the process returns to S1.

Even in the above-mentioned device, when the write command switch is pressed, the data corresponding to the decimal number "00" is written to the buffer. This will be done if the
The same effect as the device shown in FIG. 2 can be obtained.

In the above embodiment, the contents of the memory are erased when the input data corresponds to the decimal number "00", but when the input data corresponds to the decimal number "00", When loading a program into a storage device in a device that has a meaning, such as an arithmetic unit, the contents of the memory are erased when data corresponding to the maximum value, such as the decimal number "99", is input. Also good. In addition, in this example, the input data is a two-digit 10
Although the input data is 8-bit data encoded in BCD that corresponds to a hexadecimal number, the present invention also applies when the input data is 8-bit or 6-bit data that corresponds to a 2-digit hexadecimal number or a 2-digit octal number, respectively. The present invention can also be applied when the number of digits of input data is three or four digits instead of two.

As detailed above, according to the program loading method according to the present invention, input data and predetermined data are compared, and when the input data and the predetermined data match, the memory contents of the storage device into which the program is loaded are erased. Therefore, an operation switch for erasing the memory content is no longer necessary, and it is expected that the device can be easily miniaturized and the number of erroneous operations will be reduced. Furthermore, since the stored contents are erased only when a plurality of operation switches are operated in a predetermined procedure, it is possible to prevent the stored contents from being erroneously erased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an apparatus for storing a program in a storage device using a conventional program loading method, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a flowchart showing the operation of the apparatus shown in FIG. 3. Explanation of codes of main parts, 11...Encoder,
12...Register, 13...Write control circuit, 1
5...Address generation circuit, 16...Memory, 20
...Predetermined data generation circuit, 21 ... Data comparison circuit, 30 ... Timing pulse generation circuit, 31 ...
...key matrix, 32...operation switch detection circuit, 33...input port, 35...processor,
36...ROM, 37...RAM.

Claims (1)

[Claims] 1. A program loading method for storing a program that instructs a series of operations so that a plurality of songs are played according to a predetermined performance procedure in a storage device of an automatic performance player, etc., which includes input data and predetermined data. a step of comparing the input data with the predetermined data, a step of erasing the storage contents of the storage device when the input data matches the predetermined data, and a step of erasing the stored contents of the storage device when the input data and the predetermined data do not match, the input data is replaced with the instructions in the program. A method for loading a program, comprising the step of: storing the program in the storage device.