JPH0355982B2 - - Google Patents
Info
- Publication number
- JPH0355982B2 JPH0355982B2 JP57085201A JP8520182A JPH0355982B2 JP H0355982 B2 JPH0355982 B2 JP H0355982B2 JP 57085201 A JP57085201 A JP 57085201A JP 8520182 A JP8520182 A JP 8520182A JP H0355982 B2 JPH0355982 B2 JP H0355982B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor
- pad
- evaluation
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は、半導体装置の信頼性試験の用に供
される半導体評価用装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor evaluation device used for reliability testing of semiconductor devices.
従来、この種の装置として第１図に示すものが
あつた。 Conventionally, there has been a device of this type as shown in FIG.
同図において、１は半導体チツプ、２は上記チ
ツプ１に設けられた外部電極接続用パツドで、上
記チツプ１の周辺部１ａに配置されている。３は
上記チツプ１に設けられた評価用素子であり、上
記パツド２の内側部分、換言すれば上記チツプ１
の中央部１ｂに配置されている。 In the figure, reference numeral 1 denotes a semiconductor chip, and reference numeral 2 denotes an external electrode connection pad provided on the chip 1, which is arranged in a peripheral portion 1a of the chip 1. Reference numeral 3 denotes an evaluation element provided on the chip 1, which is the inner part of the pad 2, in other words, the chip 1.
It is arranged in the center part 1b of.
この半導体評価用装置を用いて、信頼性試験を
実施することにより、ストレスが半導体チツプ１
に設けられた評価用素子３に印加される。評価用
素子３に対するストレスの度合を外部電極接続用
パツド２を介して検出し、これにより該評価用素
子の電気的特性を調査していた。 By conducting a reliability test using this semiconductor evaluation equipment, stress can be reduced to a semiconductor chip.
The voltage is applied to the evaluation element 3 provided at . The degree of stress on the evaluation element 3 was detected via the external electrode connection pad 2, and thereby the electrical characteristics of the evaluation element were investigated.
ところで、温度サイクル試験、プレツシヤクツ
カ試験等の環境試験において、半導体チツプに印
加されるストレスは周辺部程大きく、中央部は小
さいものである。したがつて、従来の半導体評価
用装置では、評価用素子３が上記チツプ１の中央
部１ｂ寄りに位置しているため、ストレスが半導
体チツプ１の周辺または外部電極接続用パツド２
の部分におよんでも、検出しにくい欠点があつ
た。 By the way, in environmental tests such as temperature cycle tests and stress tests, the stress applied to a semiconductor chip is greater at the periphery and smaller at the center. Therefore, in the conventional semiconductor evaluation device, since the evaluation element 3 is located near the center portion 1b of the chip 1, stress is applied to the periphery of the semiconductor chip 1 or to the external electrode connection pad 2.
However, there were defects that were difficult to detect.
この発明は上記のような従来のものの欠点を除
去するためになされたもので、評価用素子を少な
くともストレスの影響を最も受けやすいチツプ周
辺部に配列することにより、小さなストレスでも
短時間にかつ容易に検知できる半導体評価用装置
を提供することを目的としたものである。 This invention was made in order to eliminate the drawbacks of the conventional devices as described above. By arranging the evaluation elements at least in the peripheral area of the chip that is most susceptible to stress, even small stresses can be easily and quickly processed. The purpose is to provide a semiconductor evaluation device that can detect
以下、この発明の一実施例を図面について説明
する。 An embodiment of the present invention will be described below with reference to the drawings.
第２図において、１は半導体チツプ、２は半導
体チツプ１に設けられた外部電極接続用パツド
で、上記チツプ１の中央部１ｂに位置している。
３は上記半導体チツプ１に設けられた評価用素子
であり、上記パツド２の外側部分、つまり上記チ
ツプ１の周辺部１ａに配置されている。 In FIG. 2, 1 is a semiconductor chip, and 2 is an external electrode connection pad provided on the semiconductor chip 1, which is located in the central portion 1b of the chip 1.
Reference numeral 3 designates an evaluation element provided on the semiconductor chip 1, which is disposed on the outer side of the pad 2, that is, on the periphery 1a of the chip 1.
前記半導体評価用装置を用いて種々の信頼性試
験を実施することにより、ストレスが半導体チツ
プ１の周辺部１ｂにある評価用素子３に印加され
るが、このストレスの影響は上記チツプ１の中央
部１ｂに比較して、周辺部１ａほどその影響を受
けやすい。したがつて、半導体チツプ１の周辺部
１ａに配置されている評価用素子３の特性を、外
部電極接続用パツド２を介して測定することによ
り、微少なストレスでも容易に検出できることと
なる。 By carrying out various reliability tests using the semiconductor evaluation device, stress is applied to the evaluation element 3 located at the peripheral portion 1b of the semiconductor chip 1, but the influence of this stress is The peripheral portion 1a is more susceptible to this effect than the portion 1b. Therefore, by measuring the characteristics of the evaluation element 3 disposed in the peripheral portion 1a of the semiconductor chip 1 via the external electrode connection pad 2, even minute stress can be easily detected.
前記実施例では、評価用素子３を半導体チツプ
１の周辺部１ａのみに配置した例を示したが、当
然のことながら上記チツプ１の中央部１ｂにも評
価用素子３を配置してもよいことは明らかであ
る。 In the above embodiment, an example was shown in which the evaluation element 3 was arranged only in the peripheral part 1a of the semiconductor chip 1, but it goes without saying that the evaluation element 3 may also be arranged in the central part 1b of the chip 1. That is clear.
以上のように、この発明によれば外部電極接続
用パツドを半導体チツプ中央部寄りに設け、評価
用素子を少なくとも前記パツド配設部とチツプ周
縁との間に設けることにより、ストレスの影響を
受けやすい上記チツプ周辺部の評価が容易にかつ
短時間で検出し得る半導体評価用装置を提供する
ことができる。 As described above, according to the present invention, the pad for external electrode connection is provided near the center of the semiconductor chip, and the evaluation element is provided at least between the pad placement area and the periphery of the chip, so that the chip is not affected by stress. Accordingly, it is possible to provide a semiconductor evaluation device that can easily and quickly evaluate the peripheral area of the chip.
第１図は、従来の半導体評価用装置を示す上面
図、第２図は、この発明に係る半導体評価用装置
の一例を示す上面図である。
１……半導体チツプ、１ａ……周辺部、１ｂ…
…中央部、２……外部電極接続用パツド、３……
評価用素子。なお、図中、同一符号は同一もしく
は相当部分を示す。
FIG. 1 is a top view showing a conventional semiconductor evaluation device, and FIG. 2 is a top view showing an example of a semiconductor evaluation device according to the present invention. 1... Semiconductor chip, 1a... Peripheral part, 1b...
...Central part, 2... Pad for external electrode connection, 3...
Evaluation element. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
パツドを設け、このパツドに電気的に接続され、
この接続されたパツドを介して特性を評価される
評価用素子を、前記パツド配設部と上記チツプ周
縁との間に配置したことを特徴とする半導体評価
用装置。1. A pad for external electrode connection is provided near the center of the semiconductor chip, and the pad is electrically connected to this pad.
A semiconductor evaluation device characterized in that an evaluation element whose characteristics are evaluated through the connected pads is disposed between the pad placement portion and the periphery of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57085201A JPS58200549A (en) | 1982-05-18 | 1982-05-18 | Device for evaluating semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57085201A JPS58200549A (en) | 1982-05-18 | 1982-05-18 | Device for evaluating semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58200549A JPS58200549A (en) | 1983-11-22 |
| JPH0355982B2 true JPH0355982B2 (en) | 1991-08-27 |
Family
ID=13852003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57085201A Granted JPS58200549A (en) | 1982-05-18 | 1982-05-18 | Device for evaluating semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58200549A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0740581B2 (en) * | 1987-05-18 | 1995-05-01 | 富士通株式会社 | Semiconductor integrated circuit and manufacturing method |
| JP5649478B2 (en) * | 2011-02-16 | 2015-01-07 | 三菱電機株式会社 | Semiconductor device and test method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140878A (en) * | 1974-10-04 | 1976-04-06 | Hitachi Ltd |
-
1982
- 1982-05-18 JP JP57085201A patent/JPS58200549A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58200549A (en) | 1983-11-22 |
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