JPH0356038A - Parallel operation controller for inverter - Google Patents

Abstract

PURPOSE:To continue a parallel operation with a simple circuit by employing one of a plurality of inverters as a master unit and other one as a slave unit, and using the output of an inner oscillator of the other predetermined inverter as a phase reference when the master unit becomes defective during a parallel operation. CONSTITUTION:DC power sources 1a, 1b are converted to VVVF by inverters 2a, 2b, connected in parallel through filters 3a, 3b and breakers 4a, 4b, and power is supplied to a common load 5. In this case, one such as 2a of the inverters is used as a master unit, the oscillating frequency of an oscillator 14a is selected by a selector 21a, locked by a PLL circuit 11a, and the inverter 2b is followed to the inverter 2a. When the unit 2a becomes defective, a phase reference changeover switch 21a is opened through selection signal transmitters 22a, 22b, 21b is closed, the oscillating frequency of an oscillator 14b is locked by a PLL circuit 11b as a phase reference. Thus, a simple controller which is scarcely received by a temperature drift, an aging drift, and does not need a phase correction is composed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a parallel operation control device for inverters that performs parallel operation by matching the output phases of a plurality of inverters.

(Prior art) In uninterruptible power supply systems using inverters, in order to improve their reliability, multiple inverters are often operated in parallel. In order to provide redundancy so that even one or more inverters do not affect the entire system, each inverter needs to be an independent structure with no common parts in either the main circuit or the control circuit. FIG. 3 is a block diagram showing a conventional inverter parallel operation control device of this type. In the figure, the first machine and the second machine are distinguished by adding suffixes a and b. la. lb is a DC bus, to which a DC voltage obtained by using a rectifier (not shown) for converting AC into DC, a storage battery, or a combination of both is supplied. 2a and 2b are inverters whose DC bus converts voltage into AC;
, 2b is an AC filter for improving the waveform of the inverter output into a sine wave, 4a and 4b are circuit breakers for connecting or disconnecting the inverters in parallel, and 5 is a load.

On the other hand, the control device uses a phase difference detector (PHD)
la, 11lb, low-pass filter (L P F) 11
2a, 112b. Voltage controlled oscillator (VCO) 11
3a, 113b, to a certain PLL circuit 11a, ll
b, ring counters 12a and 12b that divide the output of the PLL circuits 11a and llb to generate gate pulses for each inverter, and a PLL circuit 11a that generates a signal for correcting deviations in active power supplied by each inverter. ，
active power deviation (ΔP) detection circuits 13a, 13b and phase correction circuits 15a, 15b, which are applied to low-pass filters 112a, 112b of llb, PLL circuits 11a,
It consists of oscillators 14a and 14b which serve as phase references for llb.

Note that voltage control for correcting deviations in reactive power is actually required as control for operating the inverters in parallel, but this is omitted here.

The PLL circuit is a well-known technology, and the detailed operation of the configuration for feeding back the active power deviation of each inverter output to the PLL circuit to correct the deviation is described in Patent No. 121.
No. 5332 ``Parallel operation device for inverters'', but here, it corrects deviations in active power sharing caused by phase shifts due to frequency deviations of oscillators 14a and 14b, which serve as phase references for PLL circuits 11a and llb. It is.

(Problem to be Solved by the Invention) However, in the above configuration, each oscillator 1
Since the output frequencies of the inverters 4a and 14b do not match and the phase difference between the inverter outputs changes from time to time, it is necessary to set the gain K of the phase correction circuits 15a and 15b high to ensure sufficient phase correction. Therefore, active power deviation detection circuits 13a, 13b and phase correction circuits 15a, 15
Since the offset included in b is also amplified by a high gain K and appears, it is susceptible to temperature drift and drift over time, and it is not easy to adjust the circuit.

Further, the means for detecting the active power deviation also includes 13a,
13b and the parts exchanged between each machine, the structure is not necessarily simple, and the mutually exchanged signals are analog signals, and digitization is not easy in terms of reliability and cost.

In view of the above-mentioned points, an object of the present invention is to provide an inverter parallel operation control device with a simple structure that is less susceptible to temperature drift and temporal drift and does not require phase correction due to active power deviation. do.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an inverter that controls the output phases of a plurality of inverters connected in parallel to an output common bus and operated in parallel so that they match each other. The parallel operation control device includes a phase lock loop circuit (CPLL circuit) that controls the output phase of each inverter to be synchronized with the phase of the output common bus or the output phase of the internal oscillator of each inverter, and a phase lock loop circuit (CPLL circuit) that controls the output phase of the internal oscillator. A phase reference for switching the phase reference of another predetermined inverter from the output common bus phase to the output phase of the internal oscillator when one inverter that activates the phase of the output common bus as a phase reference is stopped or malfunctions. The inverter is provided with a switching means and a transmission line connecting each inverter to mutually transmit signals that determine the operation mode of the phase reference switching means.

(Function) In the inverter parallel operation control device with such a structure, one inverter (.IN!!) controls the internal oscillator output phase, and the other inverters (followers) control the output common bus line. When the inverter (base unit) that controls the internal oscillator output phase as a reference and energizes the output common bus phase with the internal oscillator output phase as the phase reference stops or malfunctions, the phase reference of other specified inverters is switched to the internal oscillator output phase. The output phase of each inverter is controlled by a signal on the transmission line connecting each inverter so that the output phase of each inverter always matches each other so that the inverter is used as the next master unit.

(Example) An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, parts that are the same as those in FIG. 3 are given the same reference numerals, and their explanation will be omitted, and only the different points will be described here. That is, in this embodiment, as shown in FIG. 1, phase reference changeover switches 21a and 2lb which switch the phase reference of the PLL circuits 11a and llb from the output common bus phase to the oscillators 14a and 14b, and a phase reference changeover switch 21a. , 2lb, and a selection signal transmission circuit 22a for transmitting to other machines selection information of the machine (master machine) that controls the output common bus phase to other machines.
22b.

The selection signal transmission circuits 22a and 22b mutually transmit signals between the inverters in the form of serial data used in data communications, for example.

Next, we will discuss the operation of the inverter parallel operation control device configured as described above. For example, when the No. 1 machine is started first and the breaker 4a is turned on, since there is no phase signal to be used as a reference on the output common bus before the breaker 4a is turned on, the selection signal transmission circuit 22a The phase reference changeover switch 21 is set so that the output phase of
While giving the selection signal to the internal oscillator 14a, the first machine
A signal is transmitted to the second unit indicating that it is the master unit with the phase reference being .

If the circuit breaker 4a of the machine is turned on in this state, the voltage phase of the output common bus is changed to the oscillator 14 by the PLL circuit 11a.
It is controlled to match the output phase of a. Next, when the No. 2 machine is started, the phase reference changeover switch 2lb selects the output common bus phase by the signal transmitted from the No. 2 machine via the selection signal transmission circuit 22b, and the output voltage phase of the No. 2 machine is determined by the PLL circuit 11a. Controlled to match the output common bus phase. If the breaker 4b of the No. 2 unit is turned on in this state, the output voltage phase of the No. 2 inverter becomes l.
Since the output voltage phase matches the output voltage phase of the unit, parallel operation can be performed without galvanometric current.

(In other words, the first unit that controls the phase of the output common bus is used as the master unit, and the second unit is operated in parallel as a follower unit that follows the master unit.) In addition, the selection signal transmission circuits 22a and 22b perform mutually transmitting signals. As shown in the example of FIG. 2, the data is transmitted using a serial code represented by the RS-232C interface, which is widely used in computer communications. This transmission signal includes current base unit selection information (here, machine number selection) and information on the machine that will be selected next as the base unit (here, machine number 2) when the base unit stops or has an abnormality. In particular, the latter information is important information in a parallel operation system of three or more inverters. Furthermore, this transmission signal is transmitted from the current master device to the follower device as the source, and includes a parity pit to prevent transmission errors.

Next, we will discuss the operation when Unit 1 stops or is decoupled due to some abnormality.

When the first machine stops, the selection signal transmission circuit 22a transmits the main machine stop information to the next main machine, the second machine, and the selection signal transmission circuit 22b of the second machine receives this signal via the transmission line, Internal oscillator 1 to phase reference switch 2lb
A switching command is given to make the output phase of No. 4b the phase reference, and the operation mode of the No. 2 machine is switched from the follower machine to the master machine on the transmission line, and the phase of the output common bus is controlled.

In this way, in this embodiment, the base unit and follower unit that control the output common bus phase are automatically selected by the individually provided selection signal transmission circuits 22a, 22b and phase reference changeover switches 21a, 2lb. Since the output phase of each inverter is controlled to match, parallel operation control is possible with a simple configuration that does not require phase correction due to active power deviation, and the problem of being susceptible to temperature drift and drift over time is also resolved. Ru.

In the above embodiment, control was described when two inverters were operated in parallel, but it is of course possible to obtain the same effect as described above even if three or more inverters are operated. .

Further, the selection signal transmission line between each inverter may be an optical communication system using an optical fiber from the viewpoint of noise resistance. Furthermore, the PLL circuit may be a digital PLL circuit.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an inverter parallel operation control device with a simple structure that is less susceptible to temperature drift and temporal drift and does not require phase correction due to active power deviation.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing a specific example of transmission signals between each machine in the same embodiment, and Fig. 3 is a diagram of a conventional inverter parallel operation control device. FIG. 2 is a block diagram showing a configuration example. la, Ib...DC bus, 2a, 2b...
Inverter, 3a, 3b... AC filter, 4a,
4b... Breaker, 5... Load, l
la, llb- PLL circuit, 12a, 12b・
... Ring counter, 14a, 14b... Oscillator, 21a, 2lb... Phase reference changeover switch, 22a
, 22b... selection signal transmission circuit. Figure 1 Figure 2

Claims (1)

[Claims] In an inverter parallel operation control device that controls the output phases of a plurality of inverters connected in parallel to an output common bus and operated in parallel so as to match each other, the output phase of each inverter is adjusted to match the output phase of the output common bus or each inverter. When a phase-locked loop circuit that controls to synchronize with the output phase of the internal oscillator of the inverter and one inverter that energizes the phase of the output common bus with the internal oscillator output phase as a phase reference are stopped or abnormal, phase reference switching means for switching the phase reference of another predetermined inverter from the output common bus phase to the output phase of the internal oscillator; An inverter parallel operation control device consisting of a transmission line connecting the inverters.