JPH035668B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, and in particular, a fixed mask type continuous read only memory (mask ROM) and a programmable continuous read only memory (PROM) are formed on the same semiconductor chip. The present invention relates to a semiconductor device integrated into a semiconductor device.

(b) Conventional technology and problems In conventional MIS type semiconductor devices, mask ROM is
A method of using a single-gate MIS transistor in a memory cell, implanting impurity ions into the channel region of a desired cell transistor in response to information, and changing the threshold voltage (Vth) of the transistor, or Mainly used is a structure in which information is fixed by providing or not providing an electrode contact window exposing the functional area of the transistor in an insulating film on the cell transistor.

The PROM memory cell has a floating gate or a double gate.
MIS transistors with FAMO-S structure were mainly used.

Therefore, in conventional MIS type semiconductor devices, when forming a structure in which mask ROM and PROM are installed on the same semiconductor board, due to the difference in the manufacturing method of single-gate MIS transistors and MIS transistors with FAMOS structure. There were problems in that the process became extremely complex, the manufacturing steps were lengthened, and the manufacturing yield decreased.

In addition, in the conventional structure, as mentioned above, the mask
Since MIS transistors are used in the memory cells of ROMs and PROMs, each cell occupies a large area, which limits the ability to increase the density and capacity of these ROMs.

Furthermore, in PROMs that use FAMOS transistors as memory cells, there is a problem in that the memory life is shortened due to the unavoidable leakage of charges injected into the floating gate.

(c) Object of the Invention The present invention provides a mask ROM and a memory device on the same semiconductor substrate using two types of memory elements that have a similar structure, can share most of the manufacturing steps, and occupy a small area. The present invention provides a semiconductor device formed by forming a PROM, and its purpose is to shorten the manufacturing turn of a semiconductor device in which a mask ROM and a PROM are provided on one chip, and at the same time to improve the manufacturing yield. The aim is to achieve high density and high integration of the semiconductor device.

(d) Structure of the Invention That is, the present invention provides a semiconductor device including a plurality of band-shaped second conductivity type regions arranged in line on the surface of a first conductivity type semiconductor substrate, and a plurality of band-shaped second conductivity type regions aligned on the surface of the band-shaped second conductivity type regions. an island-shaped first conductivity type region disposed, a first insulating film having an electrode contact window on the island-shaped first conductivity type region, and the strip-shaped second conductivity type region on the first insulating film. metal film wiring arranged in parallel in a direction transverse to the electrode contact window and bridging the electrode contact window, and information fixing is determined by whether or not a second insulating film is interposed within the electrode contact window. A first conductivity type polycrystalline silicon layer having a third insulating film on its upper surface is interposed in the electrode contact window, and the third insulating film is electrically short-circuited. The present invention is characterized in that a programmable read-only memory in which information is written is disposed on the same semiconductor substrate.

(e) Embodiment of the Invention An embodiment of the present invention will be described in detail with reference to the following figures.

Figure 1 shows the mask ROM installed in this embodiment.
Figure 2 is a transparent top view A and its A-A' cross-sectional view B, and Figure 3 is a transparent top view A and its A-A' cross-sectional view B of the PROM installed in the same embodiment. Schematic diagram of the arrangement of memory cells in the same embodiment, No. 4
Figures A to H are process cross-sectional views in one example of the method for manufacturing the semiconductor device shown in this embodiment.

For example, the mask ROM disposed in the semiconductor device of the present invention using an n-type silicon (Si) substrate is
As shown in Figures A and B, a plurality of strip-shaped p ⁺ -type regions 3 are separated by a field oxide film 2 on one surface of an n-type Si substrate and arranged in a vertical direction.
Island-like n ⁺ type region 4 arranged in alignment on three sides of p ⁺ type region
and an electrode contact window 5 on the island-like n ⁺ type region 4.
and 5' e.g. phosphosilicate glass (PSG)
A first insulating film 6 consisting of Si
(Although a thin oxide film is usually interposed in the region in contact with the surface, it is omitted as it is not related to the present invention), and a thin oxide film is arranged on the first insulating film 6 in a direction that crosses the band-shaped p ⁺ type region 3 at right angles, for example. A plurality of metal film wirings 7 are arranged and bridge the electrode contact windows 5 and 5'. It has a structure in which information is fixed by interposing the second insulating film 8.

In the above mask ROM, the diode formed by the island-like n ⁺ type region 4 and the band-like p ⁺ type region 3 serves as a memory cell.

Also, the PROM placed in the semiconductor device is the second PROM.
As shown in Figures A and B, similar to the mask ROM described above, island ^- like ⁿ a first insulator having a type region 3, an island-like n ^{+-type region aligned and arranged on the three sides of the strip-shaped p+ -type} region, and electrode contact windows 5 and 5' on the island-like n ⁺ -type region 4; It has a membrane 6. and the PROM
In this case, an n ⁺ -type polycrystalline Si layer pattern 9 with a thickness of about 500 to 100 [Å] is selectively arranged on the electrode contact windows 5 and 5' and is in ohmic contact with the four surfaces of the island-like n ⁺ -type regions. A third insulating film 10 made of, for example, a thermal oxide film and having a thickness of about 500 to 800 [Å] is formed on the n ⁺ type polycrystalline Si layer pattern 9, and on the electrode contact windows 5 and 5'. A plurality of metal film wirings 7 bridging the electrode contact windows 5 and 5' are disposed in a direction that crosses the band-shaped p ⁺ type region 3 at right angles, for example, so that the metal film wiring 7 and the band-shaped p ⁺ type region 3 are connected to each other. It has a structure in which information is written by applying a voltage in the forward direction during the period of time to cause destructive conduction (conducting path 11) in the third insulating film 10 of the desired electrode contact window 5'. ing.

FIG. 3 schematically shows an example of the arrangement of memory cells in a semiconductor chip having the structure of the present invention, where MR is a mask ROM arrangement area and PR is a mask ROM arrangement area.
It represents the PROM installation area.

Next, a method for manufacturing the above semiconductor device will be explained using one embodiment with reference to FIGS.

When forming a semiconductor device having the structure of the present invention, first, for example, ordinary selective oxidation (LO
-Mask ROM on n-type Si substrate 1 using COS method
Placement area (MR) surface and PROM placement area (PR)
For example, a plurality of parallel strip-shaped cell arrangement regions 12 separated by field oxide films 2 are formed on the surface. Note that a channel cut region (not shown) may be formed under the field oxide film 2. Next, using the field oxide film 2 as a mask, a p-type impurity such as boron B ⁺ is selectively implanted into the surface of the cell arrangement region 12 at a high concentration, and a desired annealing treatment is performed to form a ion-implant in the region to a depth of, for example, 1 μm. ] A band-shaped p ⁺ type region 3 is formed.

(See Figure 4A above) Next, normal chemical phase deposition (CVD) is performed on the substrate.
The film is made of a PSG film or the like using a method such as a thermal oxidation film (usually a thermal oxide film is provided at the bottom, but it is omitted in the figure) with a thickness of 0.8
A first insulating film 6 having a thickness of about 1 [μm] is formed, and then electrode contact windows 5 and 5' are formed in the first insulating film 6 by a conventional photolithography technique. Note that a plurality of electrode contact windows are formed on each strip-shaped p ⁺ type region 3 along its length.
Next, n-type impurity (e.g., arsenic As ⁺ ) is selectively implanted at a high concentration from each electrode contact window 5 and 5', and a predetermined annealing process is performed to form a 0.4 to 0.5 [μm] in the p ⁺ region 3. Forms an island-like n ⁺ type region with a depth of approximately

Note that the implantation depths of B ⁺ and As ⁺ may be changed and annealing treatment may be performed at the same time (see Figure 4 B). Next, the islands exposed in each electrode contact window 5 and 5' are formed by a normal thermal oxidation method. A second insulating film 8 made of silicon dioxide (SiO ₂ ) having a thickness of, for example, about 300 to 500 Å is formed on the 4 surfaces of the n ⁺ -type region.

(See FIG. 4C above.) Next, the mask ROM placement area MR is selectively covered with a resist film (not shown), the second insulating film 8 is washed out, and the PROM placement area is removed.
Four surfaces of the island-like n ⁺ type regions are exposed within the electrode contact windows 5 and 5' of the PR. (Refer to Figure 4 D) Next, a film with a thickness of, for example, 500 to 1000 [Å] is placed on the substrate.
An n ⁺ -type polycrystalline Si layer 9 of about 100% is formed using a doped polysilicon growth method or a method of introducing n-type impurities into non-doped polysilicon by ion implantation, etc., and then a normal photolithography technique is used. Then, an n ⁺ -type polycrystalline Si pattern 9 is selectively formed directly in contact with the island-like n ⁺ -type region 4 on the electrode contact windows 5 and 5' of the PROM arrangement region (PR). (Refer to FIG. 4, E) Next, a film is formed on the n ⁺ type polycrystalline Si layer pattern 9 to a thickness of, for example, 500 to 800 mm by, for example, a normal thermal oxidation method.
A third insulation film 10 made of a SiO ₂ film having a thickness of approximately [Å] is formed. Note that the polycrystalline Si thermal oxide film doped with impurities at a high concentration forming the third insulating film has a lower dielectric strength voltage than a normal thermal oxide film, and the above film thickness is 5 to 15 [ It is possible to destroy it with a voltage of about 100 V.

(See FIG. 4 above.) Next, the substrate surface is covered with a resist film (not shown) except for the electrode contact window 5' where predetermined information on the mask ROM region (MR) is to be fixed. The second insulating film 8 within the electrode contact window 5' is washed out to expose the surface of the island-shaped n ⁺ type region 4 within the electrode contact window 5'. (See Figure 4-G above.) Next, using a normal film wiring formation method, a mask is formed.
A plurality of metal films such as aluminum are provided on the ROM arrangement region (MR) and the PROM arrangement region (PR) to bridge the contact windows 5 and 5' in a direction that crosses the band-shaped p ⁺ type region 3 at right angles, for example. The wiring 7 is formed, and then the wiring 7 is formed in accordance with the desired write information.
Desired strip p ⁺ type region 3 of PROM arrangement region (pR)
and the desired metal film wiring 7, in the forward direction with respect to the junction between the band-shaped p ⁺ type region 3 and the island-shaped n ⁺ type region 4.
A voltage of about 15 [V] is applied to destroy the third insulating film 10 on the n ⁺ type polycrystalline Si pattern 9 disposed in the desired electrode contact window 5', and the metal film wiring 7
Information is written into the electrode contact window 5' by making the pn junction conductive between the electrode contact window 5' and the strip-shaped p ⁺ type region 3. Note that 11 in the figure indicates a conductive portion of the third insulating film. (See Figure 4-H above.) Next, although not shown, the formation of a surface protection insulating film,
After dicing and the like, the semiconductor device is completed.

(f) Effects of the Invention As is clear from the embodiments of the manufacturing method described above, by using the structure of the present invention, a mask ROM and a PROM can be manufactured on the same semiconductor substrate through a relatively simple and almost common manufacturing process. It can be installed together.

Therefore, according to the present invention, it is possible to shorten the manufacturing time and improve the manufacturing yield of a semiconductor memory device equipped with a mask ROM and a PROM.

Also, in the structure of the present invention, the diode is
Since it is used as a cell, the area occupied by the memory cell can be reduced.

Therefore, the present invention is effective in increasing the density and integration of the semiconductor memory device.

[Brief explanation of the drawing]

Figure 1 shows a mask in one embodiment of the present invention.
A transparent top view of the ROM, and a sectional view taken along the line A-A',
2 is a perspective top view A and a cross-sectional view taken along the line A-A' of the PROM in the same embodiment, FIG. 3 is a schematic diagram of the arrangement of memory cells in the same embodiment, and FIGS. 4 A to 4 are 3 is a cross-sectional view of the manufacturing process in the same embodiment. In the figure, 1 is an n-type silicon substrate, 2 is a field oxide film, 3 is a band-shaped p ⁺ type region, 4 is an island-shaped n ⁺ type region, 5 and 5' are electrode contact windows, and 6 is a first
, 7 is a metal film wiring, 8 is a second insulating film,
9 is an n ⁺ type polycrystalline silicon layer pattern, 10 is a third insulating film, 11 is a conductive part, and MR is a mask ROM
Arrangement area, PR indicates PROM arrangement area.

Claims (1)

[Claims] 1 A plurality of band-shaped second conductivity type regions arranged in line on the surface of the first conductivity type semiconductor substrate, and an island-shaped first conductivity type region arranged in alignment on the surface of the band-shaped second conductivity type regions;
a first insulating film having an electrode contact window on the island-shaped first conductivity type region; and a first insulating film having an electrode contact window disposed on the first insulating film in a direction transverse to the strip-shaped second conductivity type region. a fixed mask type successive read-only memory having a plurality of metal film wirings bridging the electrode contact window, and in which information is fixed depending on whether or not a second insulation film is interposed within the electrode contact window; A program in which a first conductivity type polycrystalline silicon layer having a third insulating film on the upper surface is interposed in the electrode contact window, and information is written by electrically shorting the third insulating film. 1. A semiconductor device characterized in that a continuous read-only memory is disposed on the same semiconductor substrate.