JPH0357322A - Improving circuit for rise time of pll - Google Patents

Abstract

PURPOSE:To improve the leading time regardless of the quantity of a control voltage in the stable state by generating a pseudo control voltage with a pseudo control voltage generating means, applying the voltage to a switching means and applying switching control with an output of the switching control means. CONSTITUTION:A PLL circuit comprising a reference signal generator 1, a phase comparator 2, an LPF 3 and a constant voltage control means 4 and a frequency divider 5 is provided with a pseudo control voltage generating means 6, a switching control means 7 and a switching means 8. Then the means 6 generates a pseudo control voltage, which is fed to the means 8 and an output from the means 7 is used to apply switching control of the means 8 thereby applying a pseudo voltage generated by the means 6 to an LPF 3. Then sum of the resistance of the means 8, 6 is selected smaller than a resistance R of the LPF 3 to charge an optional pseudo control voltage to a capacitor C for a prescribed time with a smaller time constant than that of the LPF 3. Thus, the leading time is improved regardless of the quantity of the control voltage in the stable state to improve the initial characteristic of the LPF 3.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the rise time of a PLL circuit, the purpose of the present invention is to provide a circuit that can improve the rise time regardless of the magnitude of the control voltage when stable. A PLL circuit having a comparator, a low-pass filter consisting of a resistor R and a capacitor C, a voltage controlled oscillator, and a frequency divider generates a pseudo control voltage that outputs a desired pseudo control mt pressure and has low output impedance characteristics. means, switching control means that outputs a control signal at the time of rising, and when there is a control signal from the switching control means, the pseudo control voltage is applied to the low-pass filter and the capacitor C is charged for a certain period of time. We will take precautions to improve the start-up time by providing an opening/closing means. [Industrial Application Field] The present invention relates to improving the rise time of a PLL circuit.

[Conventional technology]

FIG. 4 is a diagram showing a conventional circuit configuration, and is a diagram showing a so-called phase-locked loop circuit (hereinafter referred to as a PLL circuit). In the figure, 1 is a reference signal generator that sends out a signal with a reference frequency f, and 2 is a phase comparison that performs a phase comparison between the reference frequency fl and a comparison frequency f2, and outputs a control voltage proportional to the difference between the two frequencies. It is a vessel. Reference numeral 3 denotes a low-pass filter, which has a configuration in which a resistor Rl and a diode Di are connected in parallel, and a capacitor C1 are connected in an inverted L-shape, and mainly allows DC voltage to pass through. Note that 4 is a constant voltage controlled oscillator which inputs the control voltage of the output of the low-pass filter 3 and sends out an output of frequency ro;
is a frequency divider that divides the output of the constant voltage controlled oscillator 4 at the frequency fO and outputs a comparison signal of the resulting frequency f2. First, the PLL circuit will be explained below. The reference signal generator 1 is, for example, fl = 12.8M}lz
The output of the reference frequency is output to phase comparator 2. On the other hand, the output frequency fO (=800 to 900 MIIz) of the constant voltage i#I control oscillator 4 is fed back to the phase comparator 2, and the output of the frequency r2, which is divided by 128 by the frequency divider 5, is added. There is. Note that the following relationship exists between the error frequency Δf of the difference between the two frequencies fl and f2 applied to the phase comparator 2.

Δr=r1 −r2 = Δfs=constant Vs=kΔfs However, ΔIs is a constant error frequency Vs is the reference value of the control voltage ■ k is a proportional coefficient When the difference between these two frequencies 11 and f2 is Δfs, the constant voltage controlled oscillator 4 is controlled by the reference control voltage Vs and enters a stable operating state. That is, the reference control voltage Vs proportional to the constant error frequency Δfs is output from the phase comparator 2 and applied to the constant voltage control oscillator 4, and the constant voltage control oscillator 4 outputs a constant frequency of [0 = 800 to 900 MHz]. Send out.

Note that the state of the PLL circuit fluctuates and the constant voltage control oscillator 4
When the output frequency 10 of increases and becomes the relationship fl<[2, the error frequency Δf of the phase comparator 2 (fl-f2
．． ) becomes negative, and the control voltage V also decreases in proportion to Δf, and the control voltage from the low-pass filter 3? II voltage V is reduced to Vs-Δ■ and applied to constant voltage control oscillator 4. As a result,
The output of the constant voltage controlled oscillator 4 decreases in frequency from the reference frequency fo in proportion to the negative error voltage (-ΔV). As a result, the output frequency r2 of the frequency divider 5 also decreases in proportion to fo to Δf-0, and the PLL circuit is in a stable state Δf
Enter the -0 state. Conversely, when r1>r2, a positive error voltage (+ΔV) is output, increasing the frequency ``2'' and entering a stable state of Δf-0. Note that the low-pass filter 3 is a filter that has the characteristics of blocking high frequency components and noise and passing only a certain portion of the DC current in the control voltage. It is desirable that the CI be the desired size. However, on the output side of low-pass filter 3, capacitor C1
is connected, and the low-pass filter 3 that can control the constant voltage controlled oscillator 4 is only activated when the capacitor CI is charged at startup. This will increase the time and worsen the startup characteristics.

In order to improve the startup time of the low-pass filter 3, as shown in FIG. 4, a diode D1 is connected in parallel to the resistor R1 of the low-pass filter 3, and the voltage across the diode DI is 0. When the distance exceeds .6 to 0.7 m, the rise time is improved by bypassing the resistor Rl and charging the capacitor CI. That is, in the diagram showing the rise characteristics of the conventional circuit shown in FIG. 5, the broken line curve is the rise characteristics when there is no diode DI, and the rise stabilization time in this case is given by To. The solid line curve is the rise characteristic when the diode DI is present, and the rise time at this time is given by T1.

During these two rise times, when the control voltage Vs applied across the diode D1 exceeds 0.6 to 0.7 (ν), due to the effect of the on period of the diode Di, TI<To is always maintained. There is a relationship. On the other hand, the control 'a voltage Vs is 0.
If the distance is less than 6 to 0.7 m, the improvement effect will be lost.

[Problem to be solved by the invention]

Therefore, the rise time can be improved only when the control voltage applied to the diode inserted to improve the rise time exceeds 0.6 to 0.7 CV), and when the control voltage during stability is low, There is a problem that the effect is reduced.

An object of the present invention is to provide a circuit that can improve the rise time regardless of the magnitude of the control voltage when stable.

[Means to solve the problem]

In the present invention, as shown in FIG. 1, a reference signal generator 1,
A PLL circuit having a phase comparator 2, a low-pass filter 3 consisting of a resistor R and a capacitor C, a constant voltage controlled oscillation B4, and a frequency divider 5 outputs a desired pseudo control voltage and has a low output impedance. A characteristic pseudo control voltage generating means 6, an opening/closing control means 7 which outputs a control signal at the time of rising, and when there is a control signal from the opening/closing control means 7, the said pseudo control voltage is sent to the low-pass filter 3. In addition, an opening/closing means 8 for charging the capacitor C for a certain period of time is provided.

[For production]

In the present invention, as shown in FIG. generate a pseudo control voltage and apply it to the switching means 8,
Further, by controlling the opening and closing of the opening and closing means 8 using the output from the opening and closing control means 7, the pseudo voltage generated by the pseudo control voltage generating means 6 is applied to the low-pass filter 3.

Therefore, by selecting the sum of the resistance values of the opening/closing stage 8 and the pseudo control voltage generating means to be smaller than the resistance R of the low-pass filter 3, the capacitor C It becomes possible to charge an arbitrary pseudo control voltage for a certain period of time, and a PLL circuit with improved rise time can be realized.

〔Example〕

FIG. 2 is a diagram showing an example of the circuit structure of the present invention. In the figure, 1 to 5 are PLLs with the same configuration as the conventional circuit shown in Figure 4.
A phase comparator 2 is provided to control the difference between the output frequency fl of the reference signal generator l and the comparison frequency f2 of the frequency divider 5 to a constant level, and the control voltage generated in the phase comparator 2 is Through the filter 3, the DC control fl voltage is set,
The control voltage is applied to the constant voltage control oscillator 4 to generate a constant frequency f
This is a circuit that obtains O.

In the present invention, as shown in FIG. 2, a one-shot multi-by-break 7 that generates a gate signal as an opening/closing control means
A circuit consisting of an analog-operated switch 8 as an opening/closing means, a linear amplifier 9 as a pseudo voltage generating means, and a resistor R2 and a resistor R3 for dividing the DC voltage Vdd is provided. Further, FIG. 3 is a diagram showing the rise characteristics in the circuit of the present invention, and the portion of the invention will be explained below using FIGS. 2 and 3. DC voltage Vdd is divided by resistor R2 and resistor R3 and becomes V
Generate a pseudo control voltage of ddxR3 /R2 +R3,
The pseudo-control m voltage is input to the linear amplifier 9. The linear amplifier 9 is an operational amplifier with a small output impedance, and outputs a control voltage having the same level as the input control voltage and applies it to the switch 8. Now, for example, when the circuit is powered on and started up, for example, when a rising signal that becomes "high" at the power-on timing is manually applied to the one-shot multi-byte break 7, as shown in Figure 3 (A), As shown in (C), the control signal in Fig. 3 (B) is set to "high" only during the switch-on period t corresponding to about 90% of the stabilization time T2 of the rise of the low-pass filter 3. Output from multi-by-break 7 to switch 8,
Turn on switch 8. Therefore, the pseudo control voltage output from the linear amplifier 9 charges the capacitor CI of the low-pass filter 3 with a low output impedance via the switch 8, thereby improving the rise of the low-pass filter 3. Note that when the impedance of the switch 8 is R sw, the output impedance of the linear amplifier 9 is Rop, and the series resistance of the low-pass filter 3 is R1, the time constant of the on period of the Suinochi 8 is (Rsw + Rop) x Cl,
Furthermore, in order to improve the rise time of the low-pass filter 3, by setting Rl>Rsw+Rop, a desired improvement in the rise characteristics can be obtained.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the rise time can be improved regardless of the magnitude of the control voltage, and it is effective in improving the initial stability of the low-pass filter.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the principle structure of the present invention, FIG. 2 is a diagram showing an example of the circuit structure of the present invention, FIG. 3 is a diagram showing the rise characteristics in the circuit of the present invention, and FIG. FIG. 5 is a diagram showing a circuit configuration of a conventional example. FIG. 5 is a diagram showing a rise characteristic of a circuit of a conventional example. In the figure, 1 is a reference signal generator, 2 is a phase comparator, 3 is a low-pass filter, 4 is a constant voltage control oscillator, 5 is a frequency divider, 6 is a pseudo control voltage generation means, and 7 is a switching means (one-switch). 8 indicates opening/closing control means (swift). Circuit diagram showing the principle structure of the present invention No. 1 A diagram showing an example of the circuit structure of the present invention FIG. 2 A diagram showing the rise characteristics in the circuit of the present invention FIG. 3 A diagram showing the circuit structure of a conventional example 4 Figure

Claims (1)

[Claims] A reference signal generator (1), a phase comparator (2), and a resistor R.
and a low-pass filter (3) consisting of a capacitor C, a voltage controlled oscillator (4), and a frequency divider (5).
In the circuit, a pseudo control voltage generating means (6) that outputs a desired pseudo control voltage and has low output impedance characteristics, an opening/closing control means (7) that outputs a control signal at the time of rising, and the opening/closing control means (7). ) switching means (8) for adding the pseudo control voltage to the low-pass filter (3) and charging the capacitor C for a certain period of time;
A PLL rise time improvement circuit characterized in that the rise time is improved by providing the following.