JPH0357332A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce a cost with a comparative small memory capacity and to improve the pull in setting characteristic by providing a serial/parallel conversion section, a frame counter, a register group, a synchronous bit detection section and a discordance detection section, etc. CONSTITUTION:A register group 39 uses a serial/parallel conversion section 35 to stores an n-bit parallel signal at a specific location in inputted signals 9 converted into n-bit parallel signals by number of multi-frames (m) at every frame. Moreover, a synchronous bit detection section 15 decodes an m-bit parallel signal in the same bit location in the direction of the multi-frame outputted from the group 39 to discriminate whether or not the pattern is coincident with an expected synchronous pattern. Then a discordance detection section 19 shifts the phase of a frame counter 1 and a multi-frame counter 5 by n-bit when a signal pattern coincident with the synchronous pattern is not detected from any of n-set of m-bit parallel signals stored in the group 39 by the detection section 15 and repeats the operation sequentially. Thus, the memory capacity is reduced, the cost is reduced and the pull in setting characteristic is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame synchronization detection circuit that detects frame synchronization patterns inserted at regular intervals into a serial input signal.

[Conventional technology]

FIG. 3 shows a conventional 1-bit instant shift type frame synchronization detection circuit disclosed in "Digital Communication Technology" by Kimio Tanaka, Tokai University Press, and is considered as a first conventional example. In the figure, (1) is a frame counter that counts by the frame length, (3) is a frame pulse signal that is output for each frame, (5) is a multi-frame counter that counts multi-frames, and (7) is for each multi-frame. Multi-frame pulse signal output to (9)
is a serial input signal input externally, (11) is a multi-frame 12-bit register that latches the serial input signal (9) for each frame, and (l3) is a multi-frame register latched in register (l1). The l2 bit bit data output of (l5) is the bit data output (
13) is a synchronous bit detection unit that detects whether or not the expected synchronous bit pattern is present; (l7) is a bit data output (13
) is a synchronization bit detection signal that becomes active when the synchronization bit pattern is expected. ) is the frame counter (1) when the mismatch detection circuit (l9) detects a mismatch.
This is a counter load signal that changes the phase of the multi-frame counter and multi-frame counter (5).

Next, regarding the operation, the PCV i-order group 24c shown in FIG.
The explanation will be given according to an example of the frame format of h. In this example, 193 bits constitute one frame, and 12 frames constitute one multiframe.

When there is no serial input signal (9) from the outside, the frame counter (1) and multiframe counter (5) in the circuit are in a free running state. register (l
1) is the serial input signal (9) input manually from the outside,
Multi-frame data, that is, 12 bits of data, is latched sequentially for each frame by the frame pulse signal (3) output from the frame counter (1) that moves at an arbitrary phase.The latched data is 12-bit parallel data. It is output to the synchronous bit detection section (15) as a bit data output (l3). Synchronization bit detection section (1
5) checks whether this bit data output (13) is the expected synchronous bit pattern. If it is not the expected synchronization bit pattern, the synchronization bit detection section (15)
makes the synchronization bit detection signal (l7) inactive. The mismatch detection section (19) compares the in-circuit multiframe phase and the multiframe phase of the external serial input signal (9) for each multiframe.

When the mismatch detection unit (l9) detects a "mismatch", that is, when the multi-frame pulse signal (7) is output from the multi-frame counter (5), and the synchronization bit detection signal (17) is inactive, the frame A counter load signal (2l) is output that shifts the phase of the counter (1) and the multi-frame counter (5) by 1 bit.The above operation is repeated sequentially, and the synchronization bit detection unit (15
) detects the expected synchronization bit pattern, it activates the synchronization bit detection signal (l7). As a result, the mismatch detection section (l9) no longer detects "mismatch" and no longer outputs the counter load signal (21), so the phases of the frame counter (1) and multiframe counter (5) do not change. 5th to serial input (9)
Frame counter (1) and multi-frame counter (5) except in the case of pseudo-synchronization where the bit string in the data other than the synchronization bit position shown in the figure happens to be the same as the synchronization bit pattern and frame synchronization is detected at an incorrect position. ) always operates at this phase and has detected frame synchronization.

Next, a second conventional example will be explained with reference to FIG. This example shows a block diagram of an all-bit detection type frame synchronization circuit having a register capacity capable of storing the entire multi-frame. In the figure, (1) is a frame counter that counts by the frame length, (3) is a frame pulse signal that is output for each frame, (5) is a multi-frame counter that counts multi-frames, and (7) is for each multi-frame. (9) is a serial input signal input from the outside; (13) is a bit data output that arranges the memory contents frame by frame and sequentially outputs them as 12-bit parallel data; (15) (17) is a synchronization bit detection signal that becomes active when the bit data output (13) is the expected synchronization bit pattern; (23) is a memory that can store all bit data for multi-frames, (
25) is a frame address signal outputted from the frame counter (1) and serves as an address signal in the frame direction of the memory (23), and (27) is outputted from the multi-frame counter and is an address signal in the multi-frame direction of the memory (23). This is the multi-frame address signal.

Next, we will explain this operation. The memory (23) receives a frame address signal (25) and a multi-frame address (
All bits of the serial human input signal (9) input from the outside are sequentially stored at the address indicated by 27).

Further, the memory (23) sequentially outputs bit data output (13) as a 12-bit parallel signal in which the bit data stored above is arranged in a frame period. The synchronization bit detection unit (l5) sequentially outputs bit data (
l3) is the expected synchronization bit pattern. All bits of a multi-frame can be stored in the memory (23), and new data is latched in sequence, so if there is no bit error in the serial human input signal (9), there will always be a synchronous bit pattern somewhere. The synchronization bit detection section (15) outputs a synchronization bit detection signal (17) as soon as it detects a synchronization bit pattern.The synchronization bit detection signal (17) resets the frame counter (1) and multiframe counter (5). put on. This results in a frame pulse signal (3) and a multi-frame pulse signal (
7) is phase-synchronized with the external serial human input signal (9), which means that frame synchronization has been detected.

[Problem to be solved by the invention]

The frame synchronization detection circuit according to the 1-bit immediate shift method of Conventional Example 1 searches for a synchronization bit by shifting one bit at a time, which has the drawback of requiring a long synchronization acquisition time. Further, although the frame synchronization detection circuit using the all-bit detection method of Conventional Example 2 shortens the synchronization arching time, it requires a memory capacity for multiple frames and has the problem that the circuit becomes complicated.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a frame synchronization detection circuit which has a relatively small memory capacity, is inexpensive, and has good synchronization pull-in characteristics.

(Means for Solving the Problems) A frame synchronization circuit according to the present invention includes a serial-to-parallel converter that converts a serial human input signal having a multi-frame configuration into an n-bit parallel signal, and outputs a synchronization signal every frame period. a frame counter; a storage unit that stores m parallel signals corresponding to the number of multi-frames in synchronization with the synchronization signal, and reads bit signals at the same bit position among the m parallel signals and outputs them as m-bit parallel signals; A synchronization pattern detection unit that decodes the m-pit parallel signal at the same bit position every multi-frame period and determines whether it matches an expected synchronization pattern, and determines judgment timing for the synchronization pattern detection unit. It is equipped with a multi-frame counter that outputs a synchronization signal, and a mismatch detection section that outputs a bit signal phase shift signal to the frame counter and multi-frame counter (when the synchronization pattern detection section determines a synchronization pattern mismatch).

(Function) The storage unit in the present invention stores n-bit parallel signals at specific positions among the input signals from a line etc. that have been converted into n-bit parallel signals by the serial-parallel conversion unit, for each frame in m pieces corresponding to the number of multi-frames. m at the same bit position in the multi-frame direction output from the storage means.
The bit parallel signal is decoded to determine whether it matches an expected synchronization pattern, and the mismatch detection section detects whether the synchronization bit detection section decodes the bit parallel signal from any of the n m bit parallel signals stored in the storage means. If a signal matching the synchronization pattern is not detected, the frame counter and multiframe counter are phase-shifted by n bits, and if the expected synchronization pattern is detected, the signal is stored in the storage unit that matches the synchronization pattern. The number of the n m-bit parallel signals is determined, and the phases of the frame counter and multiframe counter are shifted by the amount corresponding to that number. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. Let us take as an example the case where 8-bit parallel data control is performed using the frame format shown in Figure 5, similar to the conventional example. In Figure 1, (1) is a frame counter that counts only the frame length, (3) is a frame pulse signal that is output for each frame, and (5) is a multi-frame or l
Multi-frame counter that counts 2 frames, (
7) is a multi-frame pulse signal that is output for each multi-frame, (9) is a serial human input signal input from the outside, (3l) is an 8-bit counter that controls parallel data, and (33) is a free-run counter (31).
), (35) is a serial/parallel converter that converts the serial input signal (9) into 8-bit parallel data, (37) is a serial/discrete converter. 8 output from (35)
A bit parallel input signal (39) is a register group that latches the parallel human input signal (37) for each frame.
(13) is the 8-bit [
- 12-bit bit data output that is sequentially output from parallel multi-frame data according to the 8-bit counter (31), (15) is the bit data output (13)
a synchronous bit detection unit that sequentially detects whether or not the synchronous bit pattern is an expected synchronous bit pattern according to an 8-bit counter (31);
(l7) is a synchronization bit detection signal that becomes active when the bit data output (l3) is the expected synchronization pattern, (
19) is a mismatch detection unit that compares the phase of the multi-frame in the circuit with the phase of the synchronization bit detection signal (17) and detects a phase shift, and (21) is when the mismatch detection unit (19) detects a mismatch. , in-circuit frame counter (+) and C
This is a count load signal that changes the phase of the manoretic frame counter (5) according to the difference between the in-circuit multiframe phase and the synchronization bit detection signal (step 7).

FIG. 2 is a diagram showing the internal circuit configuration of the register group (39) shown in FIG. is a control signal output according to the value of the counter (41), (43) is a latch that latches the bit data/event output (37) of 8-bit parallel data, (
45) extracts 1 bit of data according to the parallel data control signal (33) from each 8-bit data stored in the latch (43), and outputs 12-bit bit data (
13).

Next, operation E will be explained. When there is no serial input signal (9) from the outside, the frame counter (1) and multi-frame counter (5) are in a free running state. The 8-bit counter (31) uses the F1 norm pulse signal (3) as a trigger and performs an 8-bit counting operation from there. In this state, the serial/parallel converter (35
) is the serial input signal (9) input from the outside.
According to the parallel data control signal (33) output by the bit counter (3l), 8-bit serial/parallel conversion is performed to generate an 8-bit parallel input signal (37). The parallel input signal (37) is sequentially converted into multi-frames e and f every 7 frames by the frame pulse signal (3).
f CHa X Register group (3
9). The register group (39) extracts one bit from the stored data for each frame and outputs bit data (l3), which is 12-bit parallel data.
are output sequentially according to the operation of the 8-bit counter (31). Inside the register group (39), the parallel input signal (
37) is given as an input to 12 8-bit latches (43). The counter (4l) receives the frame pulse signal (
31) is counted up each time it becomes active, and 1
A control signal (42) is output that enables two latches (43) one by one. The latch (43) latches the parallel input signal (37) when the control signal (42) becomes active. Each selector (45
) selects one bit at the same bit position in the 8-bit data of each latch (43) according to the parallel data control signal (33), and outputs the 12-bit bit data (13).
) is output. The synchronization bit detector (15) outputs the bit data (l3
) is the expected synchronous bit pattern. If the expected synchronization bit pattern is not found in the 8 patterns of bit data output (13) sequentially output from the register group (39 registers), the synchronization bit detection unit (13)
The synchronization bit detection signal (l7) output from 5) becomes non-active. At this time, the internal multi-frame phase and external serial input signal (9) are set for each multi-frame.
Discrepancy detection unit (
19) detects that all of the eight patterns are "inconsistent" and outputs a counter load signal (21) that shifts the phases of the frame counter (1) and multiframe counter (5) by 8 bits. When the above operation is repeated sequentially and the bit data output (l3) matches the expected frame synchronization pattern, the synchronization bit detection section (l9)
Activate the synchronization bit detection signal (l7). Therefore, there is a timing at which the mismatch detection section (19) does not detect "mismatch". The mismatch detection section (l9) is
Based on the state of the 8-bit counter (31) at that time, the deviation between the multi-frame phase in the circuit and the multi-frame phase of the serial input signal (9) is recognized, and a counter load signal (21) corresponding to the deviation is generated. The phase of the frame counter (1) and multiframe counter (5) is adjusted to the frame phase and multiframe phase of the serial input signal (9).

For example, eight 1's stored in the register group (39)
If the fifth 12-bit parallel signal among the 2-bit parallel signals matches the frame synchronization pattern, 8
The bit counter (3l) is "5", and at this time, the counter load signal (21) is immediately outputted to shift the phase of the frame counter (1) and multiframe counter (5) by 5 bits. Frame synchronization is detected by the above operations.

By the way, if data with the same pattern as a synchronization bit exists in the frame shown in FIG. By providing a synchronization protection circuit which is omitted in the above embodiment, it is possible to avoid the above erroneous synchronization detection.

Although the above embodiment does not include a synchronization protection circuit, a normal protection circuit can be added as in the conventional example. In addition, the 8-bit counter (31) receives the frame pulse signal (3
Although an example in which the counter operates in synchronization with 1) is shown, the same effect can be achieved even if the counter is operated as a completely free-running 8-bit counter and a decoder is provided in the external register group (39).

In addition, although it has been explained that the mismatch detection section (19) detects only multi-frame patterns with the correct phase, the mismatch detection section (19) can also detect multi-frame patterns that are shifted in frame units. It may also be possible to output a counter load signal (21) that absorbs the deviation.

In addition, if not only one frame bit but multiple synchronization bits are inserted at regular intervals in one frame, the same effect can be obtained by increasing the capacity of the register group (39). Deepen. [Effects of the Invention] As described above, according to the present invention, serial human input signals having a multi-frame configuration are serial-parallel converted, parallel signals corresponding to the number of multi-frames are stored in the storage unit for each frame period, and each parallel signal is Bit signals at specific bit positions are output as parallel signals for multiple frames, and after decoding it is determined whether or not they match the expected synchronization pattern. High accuracy;
This has the effect of providing a frame synchronization detection circuit with short pull-in time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frame synchronization detection circuit according to an embodiment of the present invention, and FIG. 2 is a register group (39
), FIG. 3 is a block diagram of a conventional l-bit immediate shift method frame synchronization detection circuit, FIG. 4 is a block diagram of a conventional all-bit detection method frame synchronization detection circuit, and FIG. 5 is a diagram showing the frame format of PCM t-order group 24ch. (1) is a frame counter, (3) is a frame pulse signal, (5) is a multi-frame counter, (7) is a multi-frame pulse signal, (9) is a serial human input signal, (
11) is a register, (13) is a pit data output, (l
5) is a synchronization bit detection section, (l7) is a synchronization bit detection signal, (19) is a mismatch detection section, (35) is a serial/parallel conversion section, (37) is a parallel human input signal, (39)
is a register group. In addition, the same or equivalent parts in the figures are indicated by the same symbols.

Claims (1)

[Claims] a serial-to-parallel converter that converts a multi-frame serial input signal into an n-bit parallel signal; a frame counter that outputs a synchronization signal every frame period; A memory section stores m parallel signals and reads bit signals at the same bit position among the m parallel signals and outputs them as m-bit parallel signals, and decodes the m-bit parallel signals at the same bit position every multi-frame period and calculates the expected a synchronization pattern detection unit that determines whether or not the synchronization pattern matches a synchronization pattern; a multi-frame counter that outputs a synchronization signal that determines a determination timing to the synchronization pattern detection unit; and a synchronization pattern mismatch determination by the synchronization pattern detection unit. A frame synchronization circuit comprising: a mismatch detection section that sometimes outputs a bit signal phase shift signal to the frame counter and the multi-frame counter.