JPH0357342A - Communication control equipment - Google Patents

Abstract

PURPOSE:To attain the correspondence to extension of a terminal equipment without increase in number of BANs on a LAN network by deciding a CPU identifying and processing an address of a terminal equipment and having only to add a CPU in charge of processing an added terminal equipment. CONSTITUTION:A PHY section converts a signal of a LAN network into a signal level in a BAN in the BAN, a MAC section converts the signal into a parallel signal to transfer the data to a MEM section. The MAC section confirms it that a destination address is logical 0 and outputs a sender address '2' to a CPU-TBL section. The CPU-TBL references a table based on the output '2' from the MAC section to cause interrupt to a corresponding CPU number '0'. The CPU #0 uses the interrupt from the CPU-TBL and the MAC section recognizes a packet data transferred to the MEM section for the processing. Transfer is commanded to a DMAC section to apply data transfer to a host device and the end of reception is reported to the host device. The DMAC section transfers the data of the MEM section to the host device according to the command from the CPU #0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet communication control device, and particularly to a host CPU side communication control device on a LAN network.

[Conventional technology]

Conventionally, communication on packet networks such as LAN (Local Area Network) was performed using ○SI (○PEN SYS).
There is a response procedure for each layer of TEMS INTERCONECTI○N>, and data is guaranteed by these response procedures. For this reason, processing these procedures placed a considerable burden on the communication control device. In particular, the communication control device of the host CPU has multiple terminals connected to the same line, and all terminals communicate with the host. As the number of terminals increases, the communication control device on the host side runs out of processing power, and
Unable to keep up with the processing demands of the terminals, they had to add communication control devices to cope with the problem.6 [Problem to be solved by the invention] In this conventional method, communication control devices were added each time the number of terminals increased. A connection part to the LAN network, a LAN data conversion part, etc. were required for each communication control part, which wasted the H/W of all eight devices.

[Means to solve the problem]

The configuration of the communication control device of the present invention is such that the communication control device that performs packet data communication having a destination address and a source address connected to a data communication network determines the destination address of a received baguette from the communication network. A means for receiving only packets addressed to the own station, a means for receiving a packet when the source address matches a specified source address, and a CPU number corresponding to the source address for the received packet. It has a storage means, a means for outputting a processing request to a processing processor corresponding to the CPU number, and a plurality of processing processors that accept the request and perform procedural processing on the received packet. It is characterized by having a plurality of processors perform procedural processing for each step.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an example of a communication control device W (BNA) implementing the present invention.

The PHY unit that connects the physical layer with the LAN network controls the MAC layer, transfers data to the MEM in the control unit, and also outputs the source address of the received packet to the CPU TBL.The MAC unit stores transmitted and received data. Memory section <M
EM), C based on the source address output from the MAC.
A CPtJ table unit (CPU TBL) that refers to a table that stores PU numbers and generates an interrupt to the CPU corresponding to that CPU number, and a processing processor unit that processes received packets and controls data transfer with host devices. (CPU #n>, D that transfers data with the host device
It consists of a MAC section.

FIG. 2 is a configuration diagram of a LAN network in which the present invention is implemented.
The communication control unit f (BNA) under the host CPU is a LAN
*Connected to each terminal device (TMOm) via
A network address is defined for each device on the LAN network, each PNP is "O", and each terminal device is "1".
” 2”゛゛゜ has been assigned. As shown in FIG. 3, the CPU TBL in the BNA stores, in correspondence with the network address of each terminal device, the number of the processor unit in charge of processing procedures with that terminal device.

In such a LAN network, when the TMI transmits to the host, a data packet with destination address = 0 and source address -2 as shown in Figure 4 flows on the LAN network.
Packets on the N network are received by each device on the LAN network, but only the BNA with the matching destination address receives the packets, and other devices discard the packets. Within the BNA, the PHY section converts the LAN network signal to a signal level within the BNA, the MAC section converts this signal into a parallel signal, and transfers the data to the MEM section. At this time,
M.A. Part C confirms that the destination address is ゜゛O'' and sends the source address ゛゛2'' to the CPU.
Output to TBL section.

CPU TBL refers to the table based on the output "2" from the MAC section and selects the corresponding CPU number 11 0.
Generates an interrupt on ++. CPU#O is the CPU
In response to an interrupt from the TBL, the MAC unit recognizes the packet data transferred to the MEM unit and performs processing according to the procedure. When the procedure processing is completed, the CPU #O instructs the DMAC unit to transfer data to the higher-level device, and also reports the completion of reception to the higher-level device.

The DMAC section transfers the data of the MEM section to the host device according to instructions from CPU #O.

Regarding the packet from the terminal device TM3 to the host, the CPU TBL section refers to the CPU number "1" based on the source address output from the MAC section and instructs the CPU #1 to process the packet from the terminal device 3. request.

Similarly, a packet from terminal device m to the host is sent to CPU#
1 is assigned from the source address and performs packet processing.

〔Effect of the invention〕

When a terminal device is added by identifying the terminal address and determining the CPU that performs the processing, all you need to do is add the CPU in charge of the added terminal device, and the BN on the LAN network
This has the effect of being able to accommodate the addition of terminals without increasing the number of A.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a LAN#! in which the present invention is implemented. The configuration diagram of l, Figure 3 is the CPU
FIG. 4, a detailed diagram of the CPU number reference table in the TBL section, is a diagram showing the format of the packet. BNA...Communication control device connected to host CPU,
CPU#0.1...Processing processor, CPUTBL.
...CPU table section, LAN...local area network, MAC...MAC section, MEM...BN
A internal memory section, PHY/PHY section, TM○-
m...Terminal device.

Claims (1)

[Claims] In a communication control device that performs packet data communication having a destination address and a source address connected to a data communication network, means for determining the destination address of a received packet from the communication network and receiving only the packet addressed to the own station. , a means for receiving a packet when the source address matches a specified source address, a means for holding a CPU number corresponding to the source address for the received packet, and a means corresponding to the CPU number. It has a means for outputting a processing request to a processing processor that receives the request, and a plurality of processing processors that accept the request and perform procedural processing on the received packet, and has a plurality of processing processors for each transmission source or for each plurality of transmission sources. A communication control device characterized by: