JPH035792A - Synchronous oscillating circuit - Google Patents

Abstract

PURPOSE:To easily adjust a subtle defect of synchronism of a matrix display device due to the difference in device type among computers by adding a circuit, which digitally adjusts the phase of a dot clock, to a phase locked loop circuit. CONSTITUTION:In a PLL circuit (phase-locked loop circuit) 2 which generates the dot clock signal synchronized with the horizontal synchronizing signal of a video signal, a control circuit 1 as the programmable pulse generating circuit which has a charge pump 11 in the output and can generate an arbitrary pulse width is connected to the connection point between a charge pump 6 and a low pass filter 8. The phase of the dot clock as the output of a voltage controlled oscillator 3 is arbitrarily rotated to the video signal synchronized with the horizontal synchronizing signal. Thus, the matrix display device is adjusted to the synchronized display state regardless of a subtle phase deviation between the video signal and the horizontal synchronizing signal due to the difference in device type among computers.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to the door of a matrix display device such as a liquid crystal display device connected to a computer (such as an IBM PC) that does not output a dot clock synchronized with a video signal. This invention relates to a synchronous oscillation circuit for generating oscillation.

[Summary of the invention]

This invention enables fine adjustment of the phase of the synchronous oscillation circuit in the synchronous oscillation circuit of a matrix display device. It is an object of the present invention to provide a synchronous oscillation circuit that can adjust a matrix display device to a synchronized display state.

[Conventional technology]

A conventional synchronous oscillation circuit (PLL circuit 2) has a configuration shown in FIG. The PLL circuit 2 includes a VC03 (voltage controlled oscillator), a programmable counter 4, a phase comparator 5, a charge pump 6, a resistor 7, and a low-pass filter 8. In this circuit, in synchronization with the horizontal synchronization signal Sl,
Don't clock S2 can be generated. However, there is no function to adjust the phase relationship between the horizontal synchronizing signal S1 and the dot clock S2.

[Problem to be solved by the invention]

Therefore, in this method, even if computers are of the same series, there are slight differences in the video signal and horizontal synchronization signal between models, so the dot clock signal and video signal created from the video signal and horizontal synchronization signal are There is a drawback that a slight phase error occurs between the two, and as a result, it is impossible to prevent noise from occurring on the display screen of a matrix display device connected to a computer due to an error in capturing the video signal.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention adds a phase control circuit consisting of a counter, a charge pump, etc. to finely adjust the frequency of the synchronous oscillation circuit, so that the user of the display device can fine-tune the frequency of the synchronous oscillation circuit by adding a phase control circuit consisting of a counter, a charge pump, etc. This makes it possible to easily eliminate noise caused by phase errors on the display screen of a matrix display device using controls, etc.

〔Example〕

The present invention will be explained below based on FIG.

FIG. 1 is a circuit diagram of a synchronous oscillator of the present invention.

The circuit consists of a control circuit 1 and a PLL circuit 2 (phase-locked loop circuit) for controlling the frequency machine j14 according to functions. The PLL circuit 2 has a circuit configuration similar to that of a conventional single oscillation circuit. On the other hand, the control circuit 1 includes a programmer pull counter 9, a D-FFIO (flip-flop) for pulse generation, a charge pump circuit 11, a resistor 12, gates 13, 14, 15, 16, and the like.

Next, the operation of the synchronous oscillation circuit will be explained using FIGS. 1 and 3. The PLL circuit 2 generates a dot clock S2 which is multiplied by the frequency division ratio of the programmable counter 4 set by the program data S3 of the horizontal synchronizing signal S1.

Conversely, the frequency division ratio of the programmable counter 4 is a value indicating how many pulses of the dot clock S2 are present in one cycle of the horizontal synchronizing signal S1, corresponding to the display percentage of the computer.

If dot clock S2, which is the oscillation clock of VCO3,
When the frequency of the dot clock S1 is about to increase beyond the product of the frequency division ratio of the programmable counter 4 and the frequency of the horizontal synchronization signal S1, the phase difference between the horizontal synchronization signal Sl and the clock obtained by dividing the dot clock S2 is detected by the phase comparison H5, and the clock frequency is increased. The down signal CD momentarily changes from the T level (high level) to the L level (low level) in synchronization with the horizontal synchronizing signal Sl, and in response, the charge pump circuit 6 momentarily changes from the H2 state Li (high impedance state) to the H level. level.

This H level signal is applied to the oscillation frequency voltage control input of the VCO 3 via the resistor 7 and the low-pass filter 8 as a DC voltage lower than before. As a result, the oscillation frequency of the VCO 3 changes in a decreasing direction. Furthermore, if the frequency of the dot clock S2 is low, the frequency amplifier signal CU of the phase comparator 5 becomes low for a moment in synchronization with the horizontal synchronizing signal S1. In response to this, charge pump circuit 6 momentarily switches to H2 state M1.
(high impedance state) to L level.

Then, a DC voltage higher than before is applied to the oscillation frequency voltage control input of the VCO 3. As a result, the oscillation frequency of the VCO 3 changes in an increasing direction. A stable dot clock S2 is created by such a phase lock operation.

A video signal from a computer or the like is taken into the display device by this dot clock S2.

However, depending on the computer, there may be a slight phase error between the video No. 13 and the horizontal synchronization signal St. Also, if the video cable connecting the computer and display device is long, noise and impedance mismatching may occur. A phase error may occur. If there is a zero phase error, the data of the video signal cannot be captured into the display device during a stable period with little noise.

Therefore, in order for the display device to correctly capture the video signal, a circuit that can control the phase of the dot clock signal by ±1806 or more is required. This circuit is the control circuit 1. The initial setting of the control circuit 1 is to set how many times the phase of the dot clock S2 should be rotated using 4-bit data from the phase set input s4, and to set data about whether to advance or delay the phase using the phase code input S5. Do by doing.

The operation of the circuit is such that when the horizontal synchronizing signal is at H level, the data of the phase cent input S4 is read into the programmable counter 9. Then, at time tl when the horizontal synchronization signal changes from the H level to the L level, the output Q of the D-FFIO changes from the L level to the H level. When the programmer pull counter 9 counts the shift clock S6 by the number of data of the phase cent human power S4, the carrier output CO becomes H level only for one cycle of the shift clock S6. This carried output CO resets the D-FFIO.

As a result, the Q output of the D-FFIO changes from the H level to the L level at time t2. The output Q of the D-FFIO becomes a pulse with a time width from time t1 to time t2 set by the phase set input S4. This output Q is transmitted to the charge pump 11 through the gate 14 or 15 which is opened by the phase sign input S5. This charge pump 11 is not in a high impedance state but is in an H level or an L level only when the output Q is at an H level. The output S7 of the charge pump 11 is applied to the voltage addition point S8 of the PLL circuit 2 via the resistor 12. The voltage fluctuation at the voltage summing point S8 is applied to the frequency voltage control input of the VCO 3 via the low-pass filter 8. As a result, the amount of rotation of the 0 phase, in which the oscillation frequency of the VCO 3 slightly increases or decreases and the phase relationship between the dot clock S2 and the horizontal synchronizing signal Sl changes, is determined by the width of the pulse applied to the voltage addition point S8 and the amount of voltage fluctuation. ! The influence of the amount of pressure fluctuation is set by the ratio of resistance 7 and resistance 12. Typically, resistor 12 is set to a value several orders of magnitude larger than resistor 7.

By the way, when the width of the phase set human power S4 is O (all at L level), the gate 14 and the gate 15 are closed by the action of the gate 16, and the output of the charge pump 11 is always in a high impedance state. That is, when the phase is not rotated, the control circuit 1 is in a state separated from the PLL circuit 2.

In the embodiment described above, by applying a charge pump pulse signal that can be controlled in 16 steps of pulse width, for example, to the voltage addition point of the PLL circuit, the phase of the dot clock, which is the output of the voltage controlled oscillation circuit, can be adjusted. ±180
°Adjustable synchronous oscillation circuit can be constructed.

〔Effect of the invention〕

As explained above, by adding a circuit that can digitally adjust the phase of the dot clock to the PLL circuit, the present invention allows the user to easily correct subtle synchronization failures in matrix display devices that occur due to differences in computer models. Since it can be adjusted, the display device can be connected to many computers.

2・・・ ・　S　　　・ S2・ S4・ S5・ PLL circuit Horizontal sync signal dot clock phase set manual Phase code input

Claims (1)

[Scope of Claims] In a PLL circuit that includes a voltage controlled oscillator, a programmable counter, a phase comparator, a charge pump, and a low-pass filter and generates a dot clock signal synchronized with a horizontal synchronization signal of a video signal, the charge pump and the low-pass By creating a circuit configuration in which a control circuit, which is a programmable pulse generation circuit capable of generating an arbitrary pulse width and has a charge pump at the output, is connected to the connection point of the filter, the dot clock, which is the output of the voltage controlled oscillator, is connected. A synchronous oscillation circuit, wherein the phase of the oscillation circuit can be arbitrarily rotated with respect to a video signal synchronized with the horizontal synchronization signal.