JPH06164376A - Pll circuit - Google Patents

Abstract

PURPOSE:To attain the output of a clock signal with a stable waveform by providing a delay circuit to a reference signal input side of a phase comparator. CONSTITUTION:A phase comparator 3, an LPF(low pass filter) 5, a VCO(voltage controlled oscillator) 6 are arranged in this order, a frequency divider 7 to frequency-divide an output signal and to apply the resulting signal to the phase comparator 3 is provided to an output of the VCO 6 and a delay circuit 2 for phase adjustment is provided to the reference signal input. Since the phase of the reference signal with a wide pulse width is adjusted, the effect of the circuit 2 onto a change in the pulse width is avoided and the output signal from the VCO 6 is outputted without changing the pulse width. Thus, a stable clock signal is obtained without deterioration in the duty ratio and a video data signal is more accurately latched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit as a clock signal generator.

[0002]

2. Description of the Related Art Conventionally, for example, as a circuit for generating a reference signal when performing data processing on a liquid crystal display or the like,
For example, as shown in FIG. 5, a phase comparator 23, a charge pump 24, a low pass filter (hereinafter referred to as LPF) 25, a voltage controlled oscillator (Voltage).
Controlled Oscillator: Hereinafter referred to as VCO) 2
6, PLL (Phase consisting of frequency divider 27 and delay circuit 22
There is a Locked Loop circuit 21.

The phase comparator 23 uses, for example, a horizontal synchronizing signal in a liquid crystal display as a reference signal (RIN) and a signal obtained by dividing the output signal of the VCO 26 by the frequency divider 27 as a variable signal (VIN). It detects the phase difference by comparing the phases of RIN and VIN,
The phase is locked when the phase difference between RIN and VIN falls within a certain range. In addition, the charge pump 24, by the phase difference by the phase comparator 23,
For example, a UF signal is output when the phase of RIN leads the phase of VIN, and a DF signal is output when the phase of VIN leads the phase of RIN.
The signal at this time is output as an error voltage to the LPF 25, only the high frequency component is removed by the LPF 25, and output as a control voltage to the VCO 26.

Further, the VCO 26 oscillates a free-running frequency and is controlled so that the free-running frequency approaches the frequency of RIN when the control voltage is applied. When the phase is locked by the phase comparator 23, the output signal from the VCO 26 is output to the delay circuit 22 and the phase is adjusted so that the video data signal in the liquid crystal display can be latched, for example. .

In the above configuration, when the phase is locked by the phase comparator 23, as shown in FIG.
The rising edge of the 6 output signal coincides with the falling edge of the horizontal synchronizing signal RIN, and the VCO 26 output signal is output to the delay circuit 22 and the phase thereof is adjusted so that the video data signal can be latched and the clock signal is output. Is output as.

[0006]

By the way, the VCO 26
As shown in FIG. 7, the output signal has its phase adjusted at the rising point d of the VCO 26 output signal by the delay circuit 22,
The output signal is the delay circuit 22 with the point e as the rising point. However, in general, the delay circuit 22 has a characteristic that when the output signal of the VCO 26 is delayed, a difference easily occurs between the rising time and the falling time. Therefore, in many cases, the delay circuit 22 output signal Pulse width f
Becomes smaller than the pulse width of the VCO 26 output signal, and the duty ratio tends to decrease. V at low frequencies
Since the pulse width of the CO26 output signal is relatively large, the rate of decrease of the duty ratio is small even after being delayed by the delay circuit 22. Pulse width becomes smaller, the duty ratio decreases more, and sometimes the signal cannot be output, which causes malfunction.

Therefore, the VCO 26 output signal is delayed by the delay circuit 2.
If the phase is adjusted by 2, the pulse width changes, so
The video data signal cannot be accurately latched, resulting in a problem that the liquid crystal display cannot be displayed correctly.

The present invention has been made in view of the above problems, and an object thereof is to provide a PLL circuit which generates a stable clock signal such that the waveform of the signal does not change even if the phase is adjusted. Especially.

[0009]

The PLL circuit of the present invention is
A phase comparator, a low-pass filter, and a voltage-controlled oscillator are sequentially arranged, and an output side of the voltage-controlled oscillator is provided with a frequency divider for dividing the output signal and supplying it to the phase comparator. A delay circuit for adjusting the phase is provided on the reference signal input side of the phase comparator.

[0010]

With the above configuration, since the delay circuit is provided on the reference signal input side of the phase comparator, the phase adjustment can be performed on the reference signal, so that the clock signal output from the voltage controlled oscillator can be adjusted. On the other hand, it is not necessary to adjust the phase, and it is possible to prevent the duty ratio of the clock signal from decreasing. Therefore, it is possible to always output a clock signal having a stable waveform.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following will describe one embodiment of the present invention with reference to FIGS.

A PLL (Phase Locked Loo) according to this embodiment
p) The circuit 1 includes, as shown in FIG. 2, an amplifier 8 for amplifying a video data signal, an A / D converter 9 for converting an analog signal from the amplifier 8 into a digital signal, and an A / D converter
A liquid crystal including a data processing circuit 10 for performing image data processing on the digital signal from the D converter 9 and a liquid crystal display panel 11 for displaying the liquid crystal by turning on / off the liquid crystal according to an output signal from the data processing circuit 10. It is used in displays. Further, the PLL circuit 1 includes an amplifier 12
The horizontal synchronizing signal amplified by is processed to output a clock signal, which is supplied to the circuit of the liquid crystal display. This clock signal is used as a reference signal in the A / D converter 9, the data processing circuit 10 and the like. used.

Among them, the PLL circuit 1 is, for example, as shown in FIG. 1, a delay circuit 2, a phase comparator 3, a charge pump 4, a low pass filter (hereinafter referred to as LPF) 5, a voltage control. Oscillator (Voltage Co
ntrolled Oscillator: hereinafter referred to as VCO) 6 and frequency divider 7.

The delay circuit 2 uses, for example, a horizontal synchronizing signal in a liquid crystal display as a reference signal (RIN).
The phase of RIN is changed so as to latch the video data signal in the liquid crystal display.

Further, the phase comparator 3 is a variable signal (VIN) obtained by dividing the signal from the VCO 6 by the frequency divider 7 with RIN whose phase is changed by the delay circuit 2.
The phase difference between RIN and VIN is locked if the phase difference between RIN and VIN falls within a certain range. On the other hand, if the phase difference detected by the phase comparator 3 is not within a certain range, the charge pump 4 causes the phase difference of the phase comparator 3 to cause the phase of RIN to advance from the phase of VIN. When the phase of VIN is ahead of the phase of RIN, a DF signal is output when the UF signal is output. The signal at this time is output to the LPF 5 as an error voltage, only the low frequency component is extracted by the LPF 5 and output to the VCO 6 as a control voltage.

The VCO 6 oscillates at a free-running frequency. When a control voltage is generated in the LPF 5, the VCO 6 is converted into a frequency based on this control voltage. The converted frequency is divided into 1 / n by the frequency divider 7 and then output to the phase comparator 3. At this time, the phase of the VCO6 output signal is such that the falling edge of the phase-locked VIN is the rising edge of this VCO6 output signal.

Now, the output of the clock signal as the reference signal in the video data signal processing of the liquid crystal display by the PLL circuit 1 will be described below with reference to FIGS. 1 and 3.

First, as shown in FIG. 1, the PLL circuit 1
The horizontal synchronizing signal of the liquid crystal display, which becomes the reference signal RIN in FIG. It At this time, as shown in FIG. 3, the falling point a of the horizontal synchronizing signal RIN is delayed by the delay circuit 2 to the point b.

Next, the VCO frequency-divided by the frequency divider 7
Six output signals, that is, a variable signal (VIN) is output to the phase comparator 3 and is phase-compared with the output signal of the delay circuit 2. At this time, the output signal of the delay circuit 2 and the variable signal VIN
If the phase difference between and becomes a certain range, the phase is locked,
The falling point b of the output signal of the delay circuit 2 and the VCO 6
The rising point c of the output signal coincides. V at this time
The CO6 output signal is used as a clock signal used in the video data signal processing.

The clock signal output from the PLL circuit 1 is used as a reference signal when the video data signal is A / D converted in the A / D converter 9, as shown in FIG. , And is used as a reference signal when processing various image data in the data processing circuit 10.

By the way, normally, the delay circuit 2 has a characteristic that when a signal is delayed, a difference easily occurs between the rising time and the falling time. Therefore, when the phase of the signal is adjusted by the delay circuit 2, the pulse width of the signal after the phase adjustment tends to be small and the duty ratio tends to be poor. For example, the pulse width of a clock signal with a frequency of 28 MHz is about 17 If the time difference between the rising and falling edges by the delay circuit 2 is 10 ns at 0.5 ns, the pulse width after the phase adjustment becomes 7.5 ns, and a malfunction occurs in the system using this clock signal.

Therefore, by providing the delay circuit 2 on the input side of the reference signal RIN of the phase comparator 3 as in the present invention, the horizontal synchronizing signal which is the reference signal RIN so that the video data signal can be correctly latched. Since the phase can be adjusted with respect to, the phase can be adjusted without changing the pulse width of the clock signal output from the PLL circuit 1. Further, since the pulse width is not changed, the duty ratio is stable and the video data signal can be latched more correctly.

Further, in the conventional case, when the phase is adjusted, the phase of the output clock signal is directly adjusted, so that the time difference between rising and falling becomes a problem, and the frequency of the output signal by the VCO 6 is limited to 29 MHz. Only eight steps for phase adjustment could be performed, and accurate phase adjustment could not be performed. However,
In the present embodiment, the phase adjustment is performed on the low-frequency horizontal sync signal having a relatively long pulse width, so that the VCO 6 does not need to perform the phase adjustment on the output signal, and the time difference between the rising edge and the falling edge in the phase adjustment can be eliminated. It does not become a problem, and the upper limit of the output signal by VCO6 (about 40 MH
It is possible to adjust the phase up to z), and it is possible to freely increase the number of steps for the phase adjustment (16 steps in this embodiment).

By the way, in the case where the delay circuit for phase adjustment has improved characteristics, the time difference between the rising and the falling is small, so that even if the phase of the clock signal is directly adjusted, the pulse width is not so much influenced and stable. It is possible to output a signal having a waveform. However, a delay circuit having good characteristics is expensive, which increases the manufacturing cost of the entire device. However, according to the present invention, even in a delay circuit having poor characteristics, since the clock signal is not directly phase-adjusted, the problem of a time difference between rising and falling in the delay circuit does not occur. Therefore, since an inexpensive delay circuit can be used, the manufacturing cost of the entire device can be reduced.

[0025]

As described above, the PLL circuit of the present invention has the following features.
A phase comparator, a low-pass filter, and a voltage-controlled oscillator are sequentially arranged, and an output side of the voltage-controlled oscillator is provided with a frequency divider for dividing the output signal and supplying it to the phase comparator. In this configuration, a delay circuit for adjusting the phase is provided on the reference signal input side of the phase comparator.

Since the phase is adjusted with respect to the reference signal having a relatively wide pulse width, the delay circuit has no influence on the change of the pulse width and the pulse width of the output signal from the voltage controlled oscillator can be changed. It is possible to output the image data signal more accurately, and as a result, a stable clock signal can be obtained without lowering the duty ratio and the video data signal can be latched more accurately. Moreover, since a conventional delay circuit can be used, the manufacturing cost of the entire device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a liquid crystal display having the PLL circuit shown in FIG.

FIG. 3 is an explanatory diagram showing phase comparison of horizontal synchronizing signals by the PLL circuit of FIG.

FIG. 4 is an explanatory diagram showing a relationship between a signal output from the PLL circuit of FIG. 1 and a video data signal.

FIG. 5 is a block diagram of a conventional PLL circuit.

6 is an explanatory diagram showing phase comparison of horizontal synchronization signals by the PLL circuit of FIG.

7 is an explanatory diagram showing a relationship between a signal output from the PLL circuit of FIG. 5 and a video data signal.

[Explanation of symbols]

 1 PLL Circuit 2 Delay Circuit 3 Phase Comparator 4 Charge Pump 5 LPF (Low Pass Filter) 6 VCO (Voltage Controlled Oscillator) 7 Frequency Divider 9 A / D Converter 10 Data Processing Circuit 11 Liquid Crystal Display Panel

Claims (1)

[Claims] 1. A phase comparator, a low-pass filter, and a voltage controlled oscillator are arranged in this order, and a frequency divider for dividing an output signal on the output side of the voltage controlled oscillator and supplying it to the phase comparator. Circuit and a delay circuit for adjusting the phase of the output signal, wherein the delay circuit is provided on the reference signal input side of the phase comparator. .