JPH0358030A - Production of thin-film transistor array - Google Patents

Abstract

PURPOSE:To eliminate shorting by laminating light transparent connecting electrodes formed simultaneously with picture element electrodes under plural non-light transparent gate electrodes and thereby constituting gate lines. CONSTITUTION:The light transparent picture element electrodes 2 consisting of ITO and the connecting electrodes 12 are provided on a transparent substrate 1. The non-light transparent gate electrodes 3 consisting of Cr are deposited in superposition on the electrodes 12 to constitute the gate lines 4. A gate insulating film 5, a semiconductor 6 and a passivation film 7 are laminated and after a positive resist is applied thereon, the resist is exposed from the rear surface and is etched by development to form the patterns of passivation. The entire surface of the substrate 1 is coated with an impurity semiconductor film 8 and is so etched that the film 6 and the film 8 are formed across the film 7; further the film 5 is partly etched to form contact holes 11 for the purpose of contact with the electrodes 2 and the source electrodes 10; further, a metallic film consisting of Al is deposited and is etched to leave the parts corresponding to the films 10 and the drain electrodes 9. Finally, the films 8 shorting between the electrodes 9 and 10 are removed by etching. The shorting of thin-film transistor (TFT) is eliminated with the smallest number of stages.

Description

Detailed description of the invention (a) Industrial application field The present invention uses a gate electrode and a gate line as a mask,
The present invention relates to a method of manufacturing a thin film transistor (TPT) array in which a bancivation pattern or a semiconductor film is formed by exposing from the back surface of a substrate.

(b) Conventional technology In order to improve product yield by reducing the number of manufacturing steps, a self-alignment method using back exposure has come to be frequently used in TPT manufacturing methods.

For example, a method of leaving a photosensitive light-shielding resin only on the Q T F T by back exposure (Japanese Patent Laid-Open No. 63-237033)
Another method is to shorten the exposure time and leave a protective insulating film pattern on the semiconductor film by exposing the entire surface from the photoresist side after back exposure (Japanese Patent Application Laid-Open No. 63-305563), and to mask the gate electrode. There is a method in which impurities are introduced into the semiconductor film by exposing it from the insulating substrate side, leaving an insulating film in the shape of a gate electrode (Japanese Patent Laid-Open No. 158875/1987). There is.

FIG. 4 shows a perspective plan view of a TPT constructed by a conventional manufacturing method.

FIG. 2 shows a perspective view in which the substrate is cut along the gate line in FIG. 4 and the source electrode side is removed.

In FIG. 2, the backside exposure from the substrate (1) leaves a semiconductor layer (6) in the shape of the gate line (4), and the adjacent drain electrode (9) has a semiconductor layer 111! It can be seen that they are connected via (6).

(c) Problems to be Solved by the Invention As a result, adjacent drain electrodes (9) are electrically connected to each other, resulting in a drain-to-drain short circuit, which deteriorates the display characteristics of the panel.

On the other hand, in order to eliminate short-circuits, an additional mask for specifying the cutting location is required in the TPT manufacturing process, which increases the number of manufacturing steps and increases manufacturing costs.

The present invention aims to eliminate short-circuits between TFTs and to eliminate the process of cutting short-circuits.

(2) Means for Solving the Problems The present invention constructs a TPT in which one or more gate lines and a plurality of drain lines intersect on a transparent insulating substrate, and a pixel electrode or a source electrode is connected to each intersection. TP that will be done
The method for manufacturing a T-array may include a step of forming a gate line by partially laminating a light-transmitting connection electrode formed simultaneously with the pixel electrode under the plurality of separated non-light-emitting gate electrodes; Multiple non-transparent gates′!
The method is characterized in that it includes a step of partially laminating a connection electrode formed simultaneously with the source electrode on the It layer to form a gate line.

(E) Operation Since the non-light-transmitting first island region is divided into one or more pieces for the ITPT, the semiconductor film formed on the first island region is separated for each TPT. However, short circuits do not occur between adjacent TFTs.

(f) Example Hereinafter, the present invention will be explained in detail based on Examples.

(Example 1) FIG. 3 shows a perspective plan view of a first example of a TPT array formed by the manufacturing method of the present invention.

? ! As shown in Figure s3, there are a pixel electrode (2) and a connection electrode (12) made of translucent ITO on a transparent insulating substrate (1), and a non-metallic electrode (12) on the connection electrode (l2). Transparent gate electrodes (3) are stacked to form a gate line.

The gate electrode (3) is grooved with * metal such as Au-Cr, Cr, Ta, etc.

FIG. 1 is a perspective view of a TPT array according to a first embodiment of the present invention, in which the substrate is cut along the gate line in FIG. 3 and the source electrode side is removed.

In FIG. 1, the semiconductor film (6) and the passivation electrode 11 (7) on the connection electrode (12) without the non-transparent gate electrode (3) are removed, and a short circuit is created in the adjacent TPT. The structure is such that it does not occur.

T of the first embodiment of the present invention in which the connection electrode is installed first
The manufacturing process of the PT array will be explained in detail with reference to the plan view shown in FIG.

In FIG. 5(a), an image electrode (2) made of translucent ITO and a connection electrode (l2) are placed on a transparent substrate (1).
will be established.

Subsequently, a gate t-pole (3) made of non-transparent Cr is deposited on the substrate (1) so as to partially overlap the connection electrode (12).

Then, as shown in FIG. 1(b), the gate line (4) connects the non-transparent gate electrode (3) and the transparent connection electrode (1).
2).

Next, a gate insulating film made of SiNx, a-S
A semiconductor film made of SiNx and a passivation film made of SiNx are laminated on a substrate, and after coating with a photoresist, the substrate is exposed to light from the back side, developed, and etched to form a passivation pattern.

After etching, the top view of the substrate with the resist removed is shown in Figure 5.
Shown in Figure (c).

By means such as over-etching, the pattern of the passivation layer (7) is formed on the gate 'WI. It is formed with a smaller pattern than pole (3).

Then, the entire surface of the substrate is covered with an impurity semiconductor film.
6) and the impurity semiconductor film (8) are subjected to bashivation II.
Etch so as to straddle IE (7).

Next is the gate! a# [Etch a part of (5) and draw a contact hole (1l)! When formed for contact between the electrode and the source electrode H, the result is as shown in FIG. 5(d).

Furthermore, after applying a 41t metal film consisting of l to the entire surface,
When the metal film is etched leaving portions corresponding to the source and drain electrodes, the result is as shown in FIG. 5(e).

Finally, the impurity semiconductor film (8) short-circuiting between the drain electrode (9) and the second t-electrode (10) is etched and removed to complete the TPT.

(Example 2) A perspective plan view of a TPT array in which connection electrodes are later formed as a second example of the manufacturing method of the present invention. Shown in Figure 46.

In FIG. 6, the gate t4 pole (3) is Au-Cr, T
IIf is made of a non-transparent metal such as a, and is formed at the same time as the contact hole (1l) between the pixel electrode (2> and the source electrode (10)) and is used for connection with the gate electrode (3).
! It is electrically connected to the connecting 1t pole (12) through the contact hole (11) between i (12).

Further, the connection electrode (12) is formed simultaneously with the drain electrode (9) and the source electrode (10), and the connection electrode (12) is formed at the same time as the drain electrode (9) and the source electrode (10).
is manufactured so that a part of the gate electrode tfi(3) overlaps with the gate electrode tfi(3).

FIG. 7 shows a sectional view of the main part of FIG. 6.

In FIG. 7, parts of the gate insulating film (5), semiconductor film (6), and passivation III (7) remaining on the non-light-transmitting gate electrode (3) on the substrate (1) due to backside exposure are removed. to form a contact hole (11), and using this contact hole (1l) to form a gate electrode (3).
and the connecting electrode (l2) are electrically connected.

The number of newly created contact holes per ITPT for gate line formation in Figures 6 and 7 is two, but since the formation of these contact holes relieves stress in the multilayer film, cracks and peeling of the film can be prevented. suppresses and stabilizes the properties of TPT.

In the first embodiment of the present invention, an example was given in which the pattern of the passivation film is shaped by exposure from the back side. It is also possible to apply this method to pattern formation of semiconductor films.

(g) Effects of the Invention According to the manufacturing method of the present invention, short-circuits in the TPT can be eliminated with a minimum number of steps without increasing the number of steps.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a TPT array of the first embodiment manufactured by the manufacturing method of the present invention in which the source electrode side is removed, and FIG. 2 is a perspective view of a TPT array manufactured by the conventional manufacturing method in which the source electrode side is removed.
A perspective view of the PT array, FIG. 3 is a perspective plan view of the TPT array of the first embodiment manufactured by the manufacturing method of the present invention,
FIG. 4 is a perspective plan view of a TPT array manufactured by a conventional manufacturing method, FIG. 5 is a manufacturing process diagram of a TPT array according to the first embodiment of the present invention, and FIG. FIG. 7 is a perspective plan view of the TPT array of the second embodiment, and FIG. 7 is a sectional view of a main part of the second embodiment manufactured by the manufacturing method of the present invention. l...Substrate, 2...Picture xi pole, 3...gate t pole, 4...gate line, 5...gate insulating film, 6...
... Semiconductor film, 7... Passivation film, 8...
Impurity semiconductor film, 9...Drain electrode, 10...Source'+4!1iA, 11...Contact hole, l
2... Connection electrode.

Claims (2)

[Claims] (1) In a method of manufacturing a thin film transistor array comprising a thin film transistor in which one or more gate lines and a plurality of drain lines intersect on a transparent insulating substrate and a pixel electrode is connected to each intersection, the gate line is A thin film transistor array comprising a plurality of separated non-transparent gate electrodes and a transparent connection electrode formed at the same time as a pixel electrode, with a part of the connection electrode overlapping under the gate electrode. manufacturing method. (2) In a method for manufacturing a thin film transistor array comprising a thin film transistor in which one or more gate lines and a plurality of drain lines intersect on a transparent insulating substrate and a pixel electrode is connected to each intersection, the gate lines are separated. A thin film transistor array comprising a plurality of non-transparent gate electrodes and a transparent connection electrode formed at the same time as a pixel electrode, with a part of the connection electrode overlapping the gate electrode. Production method.