JPH0358031A - Thin-film transistor panel - Google Patents

Abstract

PURPOSE:To stabilize characteristics of TFTs by using light transparent drain electrodes, source electrodes and display electrodes. CONSTITUTION:The gate electrodes 2 made of Cr are provided on a transparent insulating substrate 1 consisting of glass, etc., and further gate insulating films 9 consisting of silicon oxide or silicon nitride are provided. Semiconductor films 5 made of a-Si are provided on the films 9. The left side thereof is coated with the drain electrodes 6 made of ITO and the right side with the source electrodes 7 made of ITO. Drain lines 4 are laminated on a part of the electrodes 6. The contact resistance of the drain lines with drain electrodes and the contact resistance of the semiconductor films with the source electrodes and the drain electrodes are lowered in this way and the TFTs having the stable characteristics are obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to the structure of a TFT, and particularly to the structure of a TFT formed on one side of a substrate of a liquid crystal display device.

(b) Prior art FIGS. 6a-b are plan views showing a TFT substrate used in a conventional thin film transistor panel, and its A-A'
A cross-sectional view is shown (Japanese Unexamined Patent Publication No. 1982-22066).

In FIG. 6a, a gate insulation layer is formed on the gate electrode (3) on the transparent insulating substrate (1), and the gate electrode (3) is formed on the transparent insulating substrate (1).
) Semiconductor films (5) are stacked and extend in the channel direction from both ends of the gate IE electrode (3) with a size of 4 μm or less each with the gate insulating film sandwiched therebetween.

Further, on the gate insulating hood, a display electrode (8) is formed by a transparent electrode made of ITO at a distance from the semiconductor film (5).

There is a semiconductor hole (5°) at the three-dimensional intersection between the gate electrode (3) and the drain line (4) to prevent short circuits between the gate electrode (3) and the drain line (4) due to defects in the gate insulating film. ing.

The drain line (4), the drain electrode (6), and the drain electrode (7) are formed in the same layer from the same non-transparent material,
The drain line (4) and the drain electrode (6) have one shape, and the source electrode (7) is on the semiconductor [(5) and the display electrode (8), electrically connecting them.

6 is a cross-sectional view taken along line A-A' in the direction of the current path (channel) through approximately the center of the semiconductor film (5) in FIG. 6a.
Shown in Figure b.

In FIG. 6b, a gate electrode (3) and a gate insulating film (9) are laminated on a transparent insulating film substrate (1).

The semiconductor film (5) on the gate insulating film (9) extends 4 μm from both ends of the gate 'l electrode (3).

The impurity semiconductor film (1) is divided into right and left parts on the semiconductor film (5).
4) and (14') are provided, and are connected to a non-transparent drain electrode (6) and a source electrode (7), respectively.

In addition, by stacking the source electrode (7) on the display electrode (8), the signal from the drain electrode (6) can be transferred to the display electrode (
8).

(c) Problems to be Solved by the Invention The conventional example described above suppresses the increase in leakage current due to light irradiation of the TFT by suppressing the protruding width of the gate electrode of the semiconductor film to a certain limit. It has been difficult to stabilize the characteristics of the TFT because the width of the protrusion from the gate electrode is small and the positioning of the drain electrode, source electrode, and gate electrode is performed using a mask aligner.

In other words, the drain electrode does not overlap above the gate electrode,
In addition, the source electrode sometimes overlapped significantly above the gate electrode.

An object of the present invention is to provide a thin film transistor panel with a TF
T is to stabilize the characteristics of TFT while suppressing the structural factors that cause leakage due to light irradiation.

(2) Means for Solving the Problems The present invention provides a thin film transistor panel having an inverted staggered TFT on one substrate on a transparent insulating substrate such as glass or non-quality Teflon. A translucent drain electrode such as ITO and a source 1lL electrode are provided above, the source electrode and display electrode are integrally formed, and the semiconductor film is shaped by positive back exposure from the substrate side using the gate electrode as a mask. , the drain electrode and the source electrode are formed by negative back exposure from the substrate side using the gate electrode as a mask, and the channel current is The gate electrodes are overlapped with each other by less than 3 μm from the end of the gate electrode in the path direction, or one or more non-transparent drain electrodes are placed on the transparent drain electrode and source electrode of the structure. and a source electrode are stacked, and the distance between the non-light-transmitting drain electrode and the source electrode is narrower than the distance between the light-transmitting drain electrode and the source electrode.

(e) Operation By using a light-transmitting drain electrode, source electrode, and display electrode, the electrodes can be formed in a self-aligned manner with respect to the gate electrode, and the characteristics of the TFT are stabilized.

(f) Example Hereinafter, the present invention will be explained in detail based on Examples.

(Example 1) FIGS. 1a-b show a plan view of a TFT substrate used in a thin film transistor panel of the present invention, and a cross-sectional view taken along line AA' of the plan view.

In FIG. 1a, a gate line (2) made of non-transparent Cr and a gate electrode (
3), gate line (2) and drain line (4).
) A semiconductor film (5゛) is left on the three-dimensional intersection,
A semiconductor film (5) is placed above the gate electrode (3).
The drain electrode (6) and the source electrode (7) extend by less than 3 μm each from both ends of the gate electrode (3) in the channel direction.
They are formed by overlapping each other.

The width perpendicular to the channel direction of the semiconductor film (5) is the translucent I
A drain electrode 1gi (6) consisting of TO and a source electrode (
The width is the same as 7).

The display electrode (8) and the source electrode i (7) are made of the same material and shaped as one pattern.

The drain line (4) is made of non-transparent Ti/AJ! The lower Ti (15) of the drain line (4) is in direct contact with the drain electrode (6) made of ITO.

AA' approximately in the center of the semiconductor film (5) in the channel direction.
A cross-sectional view of FIG. 1a taken along the line is shown in FIG. 1b.

In Figure 1b, a transparent insulating substrate (1) such as glass
Crli on top! There is a gate electrode (3) and a gate insulating film (9) made of silicon oxide or silicon nitride.

On the gate insulating film (9), aligned with the gate electrode (2),
There is a semiconductor film (5) made of a-Si, a drain electrode (6) made of ITO covers the left side of the semiconductor film (5), and a source electrode (7) made of ITO covers the right side of the semiconductor film (5). A drain line (4) is connected to a part of the drain electrode (6).
are stacked.

A plan view of the process sequence for manufacturing a TFT having the structure shown in FIGS. 1a-b is shown in FIGS. Shown in f.

As shown in FIG. 2a, a non-optical metal is deposited on a transparent insulating substrate (1), and gate lines (2) and gate electrodes (3) are formed in the row direction by lithography.

Next, as shown in FIG. 2b, a semiconductor film (5) is placed on the transparent insulating substrate (1) on which the gate line (2) is formed. A film is formed by CVD (P-CVD), and a positive resist (10) under the trade name AZ-5200 manufactured by Suprey Co., Ltd. is coated, and then the back side is exposed from the transparent insulating substrate (1) side, developed, and etched.

The semiconductor film (5) is under the positive resist (10) and is 2μ from the outline of the gate line (2) and gate electrode (3).
It extends for about m.

Next, as shown in FIG. 2C, the positive resist (10) is peeled off, and a transparent electrode made of ITO is deposited on the gate insulating film (9) with the patterned semiconductor film (5>). Tokyo Ohkasha's product name OMR-83 negative resist (
After coating 1l), the back side is exposed from the transparent insulating substrate (1) side, developed, and etched.

The transparent electrode made of ITO is under the negative resist (11) and overlaps the gate line (2) and the gate electrode (3) within about 2 μm of their outer dimensions.

Next, as shown in FIG. 2d, a negative resist (1l) is applied.
After removing the positive resist (10), a pattern that connects and covers a portion corresponding to the display electrode (8) and a part of the gate electrode (3), and a pattern that covers a part of the gate line (2) are purchased. Then, other parts of the semiconductor film and transparent electrode are removed by etching.

Next, as shown in FIG. 2e, a positive resist (1o) is applied.
When peeled off, a rectangular semiconductor film (5) is formed as one pattern on the gate insulating film (9) along the gate line (2).
) is formed.

ITO (12) is laminated on both ends of the semiconductor p$ film (5'), and the semiconductor film (5') acts as a gate-drain short-circuit prevention film.

At the same time, a gate insulating film (
9) Drain electrode (6) as another pattern on top
A rectangular semiconductor wire (
5) is formed.

At both ends of the semiconductor layer (5), a drain electrode (6) and a source electrode (7) made of ITO having the same width in the direction perpendicular to the channel direction overlap by 2 μm from both ends of the gate electrode (3) in the channel direction. and the semiconductor 1] * (5) is 2 μm each from both ends of the gate electrode (3) in the channel direction.
The display electrode (8) extends and is formed integrally with the source electrode (7).

Finally, as shown in FIG. 2f, Ti/A2 is vapor-deposited on the gate insulating film (9) on which the display electrode (8) etc. are formed, and drain lines (4) are formed in the column direction by lithography.
).

The drain line (4) made by Ti/Ai is ITO
ITO (12
) are stacked on top of the stacked semiconductor films (5°).

Incidentally, the laminated layer at the terminal portion of the gate line (2) is removed in a timely manner to take out the electrode.

A cross-sectional view of the process order for forming the channel portion of the TFT is shown in Figure 3a-
Shown in f.

As shown in FIG. 3a, a gate electrode (3) is formed on a transparent insulating substrate (1).

Next, as shown in FIG. 3b, a positive resist (10) is applied.
A semiconductor layer (5) is formed by backside exposure using a method having an extension width α from the end of the gate electrode (3).

The extension width α is controlled to 0 to 3 μm depending on various conditions.

Next, as shown in FIG. 3C, a negative resist (l1) is applied.
Using IT. O(12) is formed by backside exposure to have an overlap width β from the end of the gate electrode (3).

The superimposition width β is controlled to 0<β×3 μm depending on various conditions.

Next, as shown in FIG. 3d, the main part of the TFT is covered with a positive resist (10) and other parts are etched.

Next, after peeling off the resist as shown in FIG. 3e, a drain line (4) is laminated on the drain ti (6) as shown in FIG. 3f, and the channel length r of the TFT is 10 μm. Complete the following TFT substrate.

(Example 2) FIGS. 4a-b show a plan view showing a part of the thin film transistor panel of the present invention, and a cross-sectional view taken along the line A-A° from the plan view.

As shown in FIG. 4a, a gate insulating film (9) is disposed on the gate line (2) and the gate electrode (3), and a drain line whose upper layer is made of Al (13) is placed on the gate insulating film (9). (4) are formed in the column direction, and the drain electrodes (6) connected to the drain lines (4) are connected to the lower rectangular IT
The source 1i pole (7) is composed of O (12) and Al (13) in the shape of a projection in the upper layer, and the source 1i pole (7) is formed by IT in the shape of a projection in the lower layer.
It consists of O(l2) and the rectangular upper layer 6,ffi(13).

A rectangular semiconductor film (5) is placed under the drain electrode (6) and source electrode (7).
6) and the source electrode (7) is the upper layer A-poor (13).
is narrower than the underlying ITO (12) layer, and the channel length γ is approximately 6 μm.

FIG. 4b shows a cross-sectional view of FIG. 4a taken along line AA' in the direction of the current path through approximately the center of the semiconductor film (5).

As shown in Figure 4b, the transparent insulating substrate (1
) A gate electrode (3) and a gate insulating film (9) are laminated on the gate insulating film (9), and an n-type a-Si semiconductor film (5) and a drain electrode made of ITO (12) are laminated on the gate insulating film (9). (6)
A source electrode (7) made of ITO (12) is formed integrally with the display electrode (8).

On the semiconductor film (5), n" type a-Si impurity semiconductor films (14) are deposited on the left and right sides by the channel length of the TFT.

The ITO (12) pattern shaped by back exposure on the impurity semiconductor film (14) and the Ti (15) and Aε (13) patterns formed together with the drain line (4) are on both sides of the TFT channel. are formed as a drain electrode (6) and a source electrode (7), respectively.

An alignment film made of polyimide (
16), a counter electrode made of ITO (12°) is placed on the opposite transparent insulating substrate (1°), and the non-display part is black for the ITFT, and the display part is in one of the three primary colors. A colored alignment film (17) made of colored polyimide is laminated.

The liquid crystal (18) is sandwiched and aligned between the alignment film (16) on the TFT substrate side and the colored alignment film (17) on the counter substrate side.

By making the spacing between the drain and source electrodes made of non-transparent Ti/Al narrower than the spacing between the drain and source electrodes made of ITO, variations in TFT characteristics due to pattern misalignment between the gate electrode, drain electrode, and source electrode can be reduced. It can be prevented.

(Embodiment 3) FIGS. 5a-b are plan views showing a part of a thin film transistor panel according to another embodiment of the present invention, and the above-mentioned plan views are shown in A-A.
' Shows a cross-sectional view taken along the line.

As shown in Figure 5a, the auxiliary capacitance electrode (
19) does not intersect with the gate line (2) and is formed on the transparent insulating substrate (1).

As shown in Figure 5b, IT is placed on the transparent insulating substrate (1).
An auxiliary capacitor electrode (19) made of O is arranged, and a auxiliary capacitor insulating film (20) made of silicon oxide is placed on the auxiliary capacitor electrode (l9).
is covered.

A TFT and a display electrode (8) are formed on the auxiliary capacitor insulation [(20), and the opposing transparent insulating substrate (1
゛) The bulk orientation state of the liquid crystal (18) is determined by the electric field between the ITO (12°) on the top and the display electrode (8).

As an example of stabilizing the characteristics of the TFTs having the structures of Examples 1, 2, and 3, the variation in the ratio of the ONi current to the OFF current of the TFT (
100σ/X σ: Standard deviation x: Average of ON and OFF current ratios [%] is shown in Table 1, which compares the variation in the ratio of ON current to OFF current of a conventional TFT.

Table 1 As shown in Table 1, the ON current and O
The ratio of FF currents is stable.

Note that if the extension width of the semiconductor film with respect to the gate electrode or the overlap width of the drain electrode and source electrode is 3 μm or more, it is difficult to stabilize the characteristics of the TFT.

(g) Effects of the Invention The structure of the TFT of Example 1 in which the drain and source electrodes are formed using transparent electrodes has the advantage of fast response speed because the electrodes have little overlap and the parasitic capacitance of the TFT is small.

The structure of the TFT of Example 2, in which the drain and source electrodes were formed by laminating a non-transparent metal on a transparent electrode, has a structure that reduces the contact resistance between the drain line and the drain electrode, and the contact resistance between the semiconductor film and the source and drain electrodes. Since it can be made small, the IR loss in the thin transistor panel is small, and it has the advantage of being compatible with large panels with a large number of pixels.

TF of Example 3 in which an auxiliary capacitance electrode is provided under the TFT with small overlap between the gate electrode, drain electrode, and source electrode
The T groove has the advantage that the switching speed of the TFT is fast and the voltage applied to the liquid crystal is gradually reduced, so that the brightness of the screen of the thin film transistor panel becomes uniform.

As described above, the present invention realizes a TFT with a fast response speed and stable characteristics in a thin film transistor panel.

[Brief explanation of drawings]

FIGS. 1a-b are a plan view showing a TFT substrate used in the thin film transistor panel of the present invention and a cross-sectional view taken along the line AA' of the same. FIGS. 2a to 2f are plan views showing the sequence of steps for manufacturing a TFT substrate used in the thin film transistor panel of the present invention. FIGS. 3a to 3f are cross-sectional views showing the steps of manufacturing a TFT substrate used in the thin film transistor panel of the present invention. FIGS. 4a and 4b are a plan view showing a part of the thin film 1 transistor panel of the present invention and a sectional view taken along the line AA' thereof. FIGS. 5a-5b are a plan view showing a part of a thin film transistor panel according to another embodiment of the present invention, and a cross-sectional view thereof taken along the line AA'. Figure 6 a-bFIM A plan view showing a TFT substrate used in an example thin film transistor panel and its A-A”
It is a sectional view on a line. 1... Transparent insulating substrate, 2... Drain line, 3
... Gate electrode, 4... Drain line, 5, 5゛... Semiconductor film, 6... Drain electrode, 7... Source electrode, 8... Display electrode, 9... Gate insulation membrane, 1
0...Positive resist, 11...Negative resist,
l2, 12゛...ITO, 13...A2, l4...
- Impurity semiconductor film, l5...Ti, 16...alignment film, 17...colored alignment film, 18...liquid crystal, 19...auxiliary capacitor electrode, 20...auxiliary capacitor insulating film, a...extension width, β...superimposition width, γ...channel length.

Claims (4)

[Claims] (1) A TFT in which a gate line and a gate electrode are stacked on a transparent insulating substrate, then a gate insulating film, a semiconductor film on top of that, and then a drain electrode, a source electrode, and a display electrode.
In a thin film transistor panel with The semiconductor film is formed by positive backside exposure from the substrate side using the gate electrode as a mask, and extends less than 3 μm from the end of the gate electrode in the direction of the current path of the channel, forming a drain electrode and a source electrode. are formed by negative backside exposure from the substrate side using the gate electrode as a mask, and are overlapped with each other by less than 3 μm from the edge of the gate electrode in the direction of the current path of the channel, and the drain line is laminated on the drain electrode. Characteristic thin film transistor panel. (2) A TFT in which a gate line and gate electrode are stacked on a transparent insulating substrate, followed by a gate insulating film, a semiconductor film on top of that, and then a drain electrode, a source electrode, and a display electrode.
In a thin film transistor panel having a thin film transistor panel, the gate line and the gate electrode are made of the same non-transparent material, and a translucent drain electrode and source electrode are formed on the semiconductor film, and one or more non-transparent materials are formed on the semiconductor film. drain electrodes and source electrodes are stacked, the distance between the transparent drain electrode and the source electrode is wider than the distance between the non-transparent drain electrode and the source electrode, and the transparent source electrode and the display electrode are stacked together. The drain line is in the same layer as the non-transparent drain electrode and source electrode, and the semiconductor film is formed by positive backside exposure from the substrate side using the gate electrode as a mask. The drain electrode and the source electrode are formed by negative backside exposure from the substrate side using the gate electrode as a mask. A thin film transistor panel characterized in that the drain line is stacked on the drain electrode with a distance of less than 3 μm from each other. (3) The thin film transistor panel according to claim 1 or 2, characterized in that a light-transmitting auxiliary capacitor electrode and an auxiliary capacitor insulating film are provided between the gate line, the gate electrode, and the transparent insulating substrate. (4) The thin film transistor panel according to claim 1 or 2, wherein the semiconductor film has an impurity semiconductor film laminated thereon which contains an impurity serving as a donor or an acceptor.