JPH03581B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a write address forming device for forming a write XY address for the memory in a radar device that once stores radar echoes and then displays them on a raster scanning display. (Prior Art) In recent years, there has been a general trend in radars to apply various processing processes to radar echoes, and to store and display echoes obtained in polar coordinates in XY coordinates for the purpose of obtaining still images. In such a case, coordinate exchange is required, but this is difficult to achieve with the method of multiplying distance, cosine, and sine due to limitations in calculation speed. High-speed processing is achieved by extracting the relevant values and cumulatively adding them in sequence (Japanese Patent Application Laid-Open Nos. 17470-1982 and 43244-1987). From a practical point of view, this kind of radar is limited in the distance direction.
256 dots and about 4096 divisions in the azimuth direction are required, and in order to specify the adjacent address on the outermost periphery without missing any address in such a state, 12 bits is theoretically required as the number of digits of the ROM. (Problem to be Solved by the Invention) However, if the circuit is constructed using 12 bits, the 1-byte (8-bit) ROM must be accessed twice to obtain the cosine and sine values, which reduces the speed. There are various problems, such as the fact that the general-purpose 8-bit microcontroller cannot be used effectively, and the number of chips required is about twice that of the 8-bit case, making it impossible to achieve miniaturization. For this reason, it is desirable to use an 8-bit ROM, but this results in a problem in that unspecified addresses, that is, address omissions, occur. FIG. 4 shows the results of an experiment regarding this point.
Figure 4 is a reproduction of a photograph of the radar display surface.
It represents the first quadrant of the display screen. However, some parts are missing. In the figure, a level signal with a signal present is written to all specified addresses in the memory and read and displayed.However, when writing, the part where the address is missing appears as a black dot because no signal is written. ing. This dot part is the part where the address is missing. Therefore, if an 8-bit ROM is simply used, the above-mentioned address dropout will cause a practical problem. One possible way to solve this problem is to shift the write address by one address in the X-axis direction every time one screen is written. According to this, as can be seen from FIG. 4, all addresses can be specified because two consecutive addresses are not missing in the axial direction. However, according to this method, since the image moves by one pixel each time one screen is formed, an error of one pixel is generated each time one screen is formed, which gives the viewer a sense of discomfort. This results in drawbacks that cannot be ignored. (Means for Solving the Problems) The present invention has been made in view of the above, and includes a write address forming device for a memory in which radar echoes are written. )
A ROM written in advance by multiplying the chord value by 2 ^{to 8} , that is, integer replacement, a reading means for reading out the contents of the ROM at an angle corresponding to the angle θ from the radar antenna reference, and a means for writing the radar echo. write timing signal generation means for generating ²⁸ write timing signals; addition means for cumulatively adding the output value of the ROM each time the write timing signal is sent; and addition means for one of the X and Y addresses. The value input to ROM is set every other rotation of the radar antenna.
The switching means is configured to be switched so that the output value becomes +1, and a matching pulse is sent out every time the cumulative addition value reaches an integral multiple of 2 ⁸ , and the matching pulse is counted and The present invention provides a write address forming device for a radar echo memory, which is configured to form a specified address on an axis (Y-axis). (Embodiment) FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a block diagram of the entire radar device equipped with the write address forming device according to the present invention. FIG. 3 is a geometric diagram illustrating the relationship between polar coordinates and rectangular coordinates. FIG. 4 is a photographic diagram showing the state of missing addresses before the present invention is implemented. In FIG. 2, 20 is a radar antenna section,
Radio wave pulses are periodically transmitted and received by a transmission trigger from a transmission trigger generation circuit 21. The transmission trigger generation circuit 21 receives the clock pulse from the clock pulse generation circuit 22, for example.
It is designed to operate using a divided pulse frequency divided by 256. 23 is an A/D converter circuit which amplifies and detects the received radar echo and then samples it with a clock pulse; 24 is a memory for one reception screen. As can be seen from FIG. 3, the memory 24 has a total address capacity of 512.times.512 in both axial directions. 25
is a write address forming circuit which also includes a coordinate conversion circuit for converting radar echoes obtained at polar coordinates R and θ into orthogonal coordinates X and Y and writing them into the memory 24.
The write address forming circuit 25 receives various data necessary for coordinate exchange, namely, a reference (for example, due north or bow) direction signal from the radar antenna unit 20, a rotation pulse generated every time a certain angle is rotated, and the above-mentioned write timing signal. A clock pulse transmission trigger is applied which acts as a clock pulse. The structure and operation of this write address forming circuit 25 will be described later with reference to FIG. The specified address obtained by the write address forming circuit 25 is guided to the memory 24 via a switch 26. 27 is a DA conversion circuit that converts the contents read from the memory 24 into an analog signal, and 28 is a display on which the analog signal is displayed. Reference numeral 29 denotes a read/display circuit that reads signals from the memory 24 and forms scanning signals for the display 28 in synchronization with the read signals. Next, the write address forming circuit shown in FIG. 1 will be explained. Note that this embodiment describes only the formation of the X number, but as can be seen from FIG. 3, this is expressed as Since they are the same, address Y (it is sufficient to treat 90-θ as a new θ)
The explanation is omitted. In the figure, 1 is a flip-flop (hereinafter referred to as FF) that alternately outputs values of 0 and 1 as a level signal each time the bow pulse (or true north indication pulse) is sent, that is, each rotation of the antenna.
2 is an angle counter that counts rotation pulses based on the bow pulse and outputs an angle θ from the reference direction. Reference numeral 3 denotes a ROM in which, for example, a sine value corresponding to the output value θ from the angle counter 2 is expressed in 8 bits and is written in a form in which the sine value is multiplied by ²⁸ , that is, replaced with an integer. This results in
The output value X _h of the ROM3 can be expressed as INT[256sinθ]. However, INT[a] is an operator representing the integer part of a. 4 is the value X _h input to both input terminals
This is an 8-bit addition circuit that adds the previous addition value. And the output value of FF1 above is 0.1
is led to the adder circuit 6, so that X _h and X _h +1 are alternately adopted as input values of the adder circuit 6 every rotation of the antenna. 5 is a latch circuit that latches the added value using a clock pulse. Therefore, the value added at a certain moment, e.g.
When X _h is latched at the next clock pulse and returned to the input side of the adder circuit 4, the new addition result (i
+1)・X Output _h . Since the adder circuit 4 is composed of 8 bits as described above, a coincidence pulse is generated at the moment when the calculated value reaches or exceeds 256. 6 is the counting capacity 512 for counting the coincidence pulses mentioned above.
is a reversible counter, and the counted value is led to the memory 24 as the X address. 7 is a quadrant detection circuit that outputs high and low levels according to the output value of the angle counter 2. That is, to explain using FIG. 3, in the first and second quadrants, since X is in an increasing direction, a high level is output, causing the reversible counter 6 to function as an adder. Conversely, in the third and fourth quadrants, it functions as a subtracter. Also, as you can see from the figure, the center 0
is equivalent to 256 as the value of X, so 256 is sent each time
It is designed to be preset to. In addition,
These relationships also apply to the Y-axis direction (not shown). Now, the following can be seen from Figure 4. As mentioned above, address omissions do not occur continuously in the axial direction.As can be understood from the geometric relationship between polar coordinates and orthogonal coordinates, address omissions do not occur near the center, but rather occur from then on to the periphery. Address omissions occur sporadically, and the number of such omissions is not large. An address designation method that takes this point into account will be described below. However, for convenience of explanation, only address X will be mentioned. (a) When the output of FF1 is 0, let the output value of reversible counter 6 be X _i . X _i = INT [X _h /256i] However, i corresponds to the number of clock pulses for writing, and is a preset value of 256 for convenience of understanding the contents.
is not taken into consideration. That is, the description will be made assuming that X _i changes from 0 to 256. (a) When the output of FF1 is 1, it can be expressed mathematically as X _i =INT[X _h +1/256i]. In the above formula, if there is no operator INT [ ], (a)
It can be said that the rate of increase in value is faster in case (a) by i/256, but depending on the existence of this operator, it can be said whether the rate of change in address is equal or greater. . And, since the maximum value of i is 256, in case (a) and case (b), in case (a) (for example, in the first quadrant), you can finally specify up to address X which is 1 larger. It becomes possible. To give an example, when i=256 at a certain angle θ _j (when X _h =128), (A)
The X address in case (a) is 128, while it is 129 in case (a). From this, it is understood that in cases (a) and (b), the maximum address difference for the same value of i (that is, the same specified timing) is 1. To summarize this, there is no difference of more than 1 in the specified address for the same i. Near the center where i is small, the rate of change is the same, that is, the same address is designated (hereinafter referred to as a timing difference of 0), but after that there are several locations where a difference of 1 number appears. You can say that. An example of the above will be explained using a table for the case where X _h =100.

【table】

【table】

【table】

【table】

[Table] In the above table, _i is extracted and shown only when the X address changes, and the timing difference is the value when the X address changes from X _j to It shows the difference between the value of _i when the address X changes from X _j to X i +1 or X j and the value of i when the X address at X _h =101 changes from X _j to X _i +1 or X _i . Also, as can be seen from the table, the values i for X _h = 100 and X _h = 101 occur simultaneously or alternately, so 1
There will be no difference beyond the address. Address Y can also be formed using the same circuit configuration as described above. However, a circuit corresponding to FF1 is not required. Of course, FF1 is address X, Y
Since it is sufficient to provide it at either one of the addresses, it is also possible to change the address on the Y address side. Further, the ROM 3 may be provided individually corresponding to X and Y, but it is possible to easily obtain the other by performing conversion taking into account Rsin (90-.theta.). (Effects of the Invention) As described above, according to the present invention, it is possible to perform coordinate transformation with high speed, versatility, and no address omission with an extremely simple circuit configuration. Also, since the same location is specified in case (a) and case (b) near the center and nearer to the center, the direction in the center part that is particularly noticeable due to the method of shifting the whole by one location as described above. The problem of errors is resolved, and addresses are changed to specifically specify addresses where address omissions occur, so it can be said that the minimum necessary corrections have been made to the original image.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a block diagram of the entire radar device including the coordinate conversion circuit according to the present invention. Third
The figure is a geometric diagram explaining the relationship between polar coordinates and orthogonal coordinates. FIG. 4 is a copy of a photograph showing the state of missing addresses before the present invention was implemented.

Claims (1)

[Claims] 1. In a write address forming device for a memory in which radar echoes received based on waves transmitted from a rotating antenna are written, a sine (cos) value for each minute angle is replaced with an integer. te8
ROM written in bits and the above for antenna rotation direction or azimuth θ
a first reading means for reading the sine (cosine) value from the ROM; and the above for the antenna rotation direction or azimuth θ.
A second reading means for reading the co(sine) value from the ROM, and at least a radar echo write timing signal.
2 A write timing signal generating means that sends out ^eight write timing signals, and a counting capacity 2 that cumulatively adds the output value of the first reading means each time the write timing signal is sent out, and outputs a coincidence signal every time the added value reaches 256. ⁸ first adding means, and a second counting capacity 28 which cumulatively adds the output value of the second reading means each time the write timing signal is sent and outputs a coincidence signal every time the added value reaches ²⁵⁶ . an adding means; a switching means for adding a value of 1 to the first digit of one of the first or second adding means every other rotation of the antenna; a first reversible counter that is preset to the center address at each time; a second reversible counter that is preset to the center address for each transmission for counting the coincidence signal from the second addition means; quadrant detection means for switching and controlling the counting directions of the first and second reversible counters by outputting a quadrant detection signal based on the above; A write address forming device for a radar memory, comprising means for guiding.