JPH0358380A - electronic equipment - Google Patents

Abstract

PURPOSE:To heighten packaging density by suppressing the increment of an area essentially and to improve electrical reliability by reducing the number of components by forming a terminating resistance element incorporated in a semiconductor memory device within the occuplied area of a semiconductor substrate. CONSTITUTION:A memory board 100 is formed by arranging plural memory devices 102 in which emitter coupled logic (E¦L) interface circuits are connected to external terminals Din for input regularly. And a data signal is inputted from an input signal line DL to the device 102 individually, and the terminating resistance element DR is connected between the terminal Din and the ECL circuit in parallel. The element DR is formed on the main plane of the semicon ductor substrate of the device 102, therefore, it is incorporated within the occu pied area of the substrate, which prevents the increment of the area occurring essentially. As a result, the packaging density of the board 100 can be heightened, and also, the electrical reliability can be improved by reducing the number of components.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electronic devices, and in particular to semiconductor memory devices.
The present invention relates to a technique that is effective when applied to an electronic device in which a plurality of memory systems are regularly arranged on a mounting board.

[Conventional technology]

A computer memory board is configured by regularly arranging a plurality of semiconductor memory devices on a mounting board as one memory system. The semiconductor memory device may be a DRAM (Dynamic RAM) if there is a need to sufficiently increase the packaging density.
Random Access Memory).

Since the increase in the arithmetic processing speed of the computer is proportional to the increase in the access time of the semiconductor storage device, the increase in the access time is an important technical point! ! Title 1
Recently, in order to speed up the access time mentioned above, ECL (E
A technology for mounting an interface circuit (n+itter coupled logic) is being studied.

As shown in FIG. 6 (block configuration diagram), a memory board 100 employing the above technology has a plurality of semiconductor memory devices (DRP.M) 102 regularly arranged on the mounting surface of a mounting board 101. Ru. Although the structure of the semiconductor memory device 102 is not clearly shown in FIG. 6, it is, for example, a semiconductor pellet (DRAM) sealed in an SOJ type resin-sealed package.

On the mounting surface of the temporary mounting board 101, input signal lines such as a common address signal line CAL, a common clock signal line (not shown), and an input data signal line DL are arranged. The common address signal line CAL transmits an address signal AD to a plurality of semiconductor memory devices 102 as a common address signal line. A terminating resistance element AR common to a plurality of semiconductor memory devices 102 connected thereto is provided at the end of this common address signal line CAL. Termination resistance element AR is connected between common address signal line CAL and power supply Vtt for the purpose of reducing reflection of input signals. The terminating resistance element AR has a resistance value of 50 (or 75') [Ω] to match the characteristic impedance of the common address signal line, and is externally attached to the mounting surface of the mounting board 101.

The common clock signal line is connected to a plurality of semiconductor memory devices 10.
A clock signal is transmitted as a common clock signal line to the two. Although not shown, a common terminating resistance element is provided at the end of this common clock signal line, similar to the common address signal line CAL. This terminating resistor element is also mounted on the mounting board 101.
is externally attached to the mounting surface.

The data input signal line DL is connected to the semiconductor memory device 102.
The input data signal is individually transmitted to the data input signal terminal Din of each semiconductor memory device 102. An ECL interface circuit is connected to the data input signal terminal Din. The data input signal transmitted through the data input signal line DL is controlled by a control device (control gate) CG. The data input signal line DL includes a semiconductor memory device 1.
Since the data input signals input to each of 02 are different,
A terminating resistance element DR is provided for each semiconductor memory device 102. Further, the data input signal line DL is connected to the semiconductor memory device 10.
Since one to four terminal resistive elements DR are arranged according to the number of data input signal lines DL, one terminal resistance element DR is provided for each number of data input signal lines DL arranged. That is, 1 to 4 terminating resistance elements DR are arranged on the data input signal line DL, depending on the number of data input signals for one semiconductor memory device 102. This terminating resistor element DR is externally attached to the mounting surface of the mounting board 101 similarly to the terminating resistor element AR.

Note that a semiconductor device equipped with an ECL interface circuit is described in, for example, Japanese Patent Laid-Open No. 171758/1983.

[Problem to be solved by the invention]

The memory board 100 shown in FIG.
A plurality of external termination resistance elements AR.01 are mounted on the mounting surface of AR. Since each DR is placed,
There was a problem that the packaging density decreased. In particular, since the terminating resistor elements DR are arranged for each semiconductor storage device 102 and in accordance with the number of data input signals, the packaging density is equivalent to the number of terminating resistor elements DR arranged. There is a large decrease in the amount of

Further, the memory board 100 includes the terminating resistance element A.
R. The mounting board 101 corresponds to the number of DRs arranged.
The number of components mounted on the mounting surface is large.

Therefore, there is a problem in that the probability of component mounting defects and the probability of component electrical connection defects increases, and the electrical reliability of the memory board 100 decreases.

An object of the present invention is to improve the packaging density in an electronic device in which a plurality of semiconductor storage devices each having an ECL interface circuit connected to an external terminal for an input signal are regularly arranged on a mounting board as one memory system. The aim is to provide the latest technology.

Another object of the present invention is to provide a technique that can improve the electrical reliability of the electronic device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In an electronic device in which a plurality of semiconductor memory devices each having an ECL interface circuit provided at an external terminal for an input signal are regularly arranged on a mounting board as one memory system,
A terminating resistor element is built in parallel between an input signal external terminal of the semiconductor memory device and an ECL interface circuit, to which a data signal or an address signal that is individually input to the semiconductor memory device is applied. This termination resistance element is formed on the main surface of the semiconductor substrate of the semiconductor memory device.

[For production]

According to the above-mentioned means, the termination resistance element built into the semiconductor memory device is formed within the area occupied by the semiconductor substrate,
Since the area of the semiconductor package can be prevented from increasing substantially, electronic The packaging density of the device can be improved. Furthermore, the number of components mounted on the mounting surface of the mounting board can be reduced and the probability of defects can be reduced, so the electrical reliability of the electronic device can be improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to an electronic device (memory board) in which a DRAM having an ECL interface circuit is mounted as a semiconductor memory device.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

The schematic structure of an electronic device (memory board) which is an embodiment of the present invention is shown in FIG. 1 (block structure diagram).

As shown in FIG. 1, a memory board (electronic device) 100
In this example, a plurality of semiconductor memory devices 102 are regularly arranged on the mounting surface of a mounting board 101 to form one memory system.

The mounting board 101 is, for example, a printed wiring board with wiring provided on the surface of an epoxy resin board. The semiconductor memory device 102 is composed of a DRAM. This semiconductor memory device 102 is a semiconductor pellet having a DRAM function sealed in, for example, a resin-sealed package.

Examples of resin-sealed packages include SOJ type, ZIP type, and D.
This can be done with a structure such as an IP type. Although not limited to this size, the semiconductor storage device 102 (its package size)
For example, 400X750 [mil] is used. The DRAM memory cell mounted on the semiconductor pellet is
1 [Bitl information is stored and memory cell selection M]
It consists of a series circuit of an FET and an information storage capacitive element.

Input signal lines such as a common address signal line CAL, a common clock signal M (not shown), and an input data signal line DL are arranged on the mounting surface of the mounting board 101. The common address signal line CAL is made up of a plurality of address signal lines, and transmits an address signal AD to a plurality of semiconductor memory devices 102 as a common address signal line. A terminating resistance element AR common to a plurality of semiconductor memory devices 102 connected thereto is provided at the end of this common address signal line CAL. Termination resistance element AR is connected to common address signal line CA
It is connected in parallel between L and the power supply Vtt. The terminating resistance element AR is formed with a resistance value of, for example, 50 (or 75) [Ω], and is externally attached to the mounting surface of the mounting board 101.

This externally attached terminating resistance element AR is, for example, approximately 300×750 mils, although the size thereof is not limited to this size. The power supply Vtt is, for example, 1.75 [V].

The common clock signal line is connected to a plurality of semiconductor memory devices 10.
A clock signal is transmitted as a common clock signal line to both. Although not shown, a common terminating resistance element is provided at the end of this common clock signal line, similar to the common address signal line CAL. This terminating resistor element is also mounted on the mounting board 101.
is externally attached to the mounting surface.

The data input signal line DL is connected to the semiconductor memory device 102.
The input data signal is individually transmitted to the data input signal terminal Din of each semiconductor memory device 102. The data input signal terminal Din is connected to an ECL interface circuit (111
) are connected. The data input signal transmitted through the data input signal line DL is transmitted by a control device (control gate) C.
Controlled by G.

FIG. 2 (equivalent circuit diagram) shows an example of the ECL interface circuit 111. ECL interface circuit 1
11 is connected to an input signal external terminal 110 arranged on the main surface of the semiconductor pellet of the semiconductor memory device 102 . E
The CL interface circuit 111 mainly includes an electrostatic breakdown prevention circuit, an ECL circuit, a logic circuit, and an output stage circuit. The electrostatic breakdown prevention circuit mainly includes a protective resistance element, an n-channel MISFET for voltage clamping, and a plurality of diode elements. Vsub is the substrate potential.

The ECL circuit is mainly composed of an npn type bibolar transistor and a resistance element. Vref is a reference potential. The logic circuit mainly consists of npn-type bibolar transistors, n-channel MISFETs, and p-channel MISFETs. Vg is a fixed potential. The output stage circuit is composed of a pull-down circuit formed of an npn type pibora transistor.

The output signal of this output stage circuit is sent to the internal circuit (Write G
an).

As shown in FIG. 1, the data input signal line DL is provided with a termination resistance element DR for each semiconductor memory device 102 because the data input signal input to each semiconductor memory device 102 is different. In addition, the data input signal line DL
For example, one to four terminal resistance elements DR are arranged depending on the number of data input signal lines DL of the semiconductor memory device 102, so a termination resistance element DR is provided for each number of data input signal lines DL arranged. That is, 1 to 4 terminating resistance elements DR are arranged on the data input signal line DL, depending on the number of data input signals for one semiconductor memory device 102.

As shown in FIGS. 1 and 2, the terminating resistance element DR
are arranged in parallel between the data input signal terminal Din and the ECL interface circuit 111. That is, the termination resistance element DR is built into the semiconductor memory device 102. This termination resistance element DR has an end connected to the data input signal terminal Din.
and the ECL interface circuit 111, and the other end is connected to an external terminal for power supply (VttB12).

The power supply Vtt applied to this external power supply terminal (vtt) 112 is, for example, 1.75 [V].

The specific structure of this terminating resistor element DR is shown in FIG. 3 (a plan view of essential parts) and FIG. 4 (a sectional view taken along the rV-IV cutting line in FIG. 3).

The termination resistance element DR is formed on the main surface of the p-type semiconductor substrate 1 (or well region), which is a semiconductor pellet of the semiconductor memory device 102, as shown in FIGS. 3 and 4.

That is, the termination resistance element DR is constituted by an n-type semiconductor region (diffusion layer) 3 formed on the main surface of the p-type semiconductor substrate 1 in a region surrounded by the field insulating film 2 . This n-type semiconductor region 3 is for example an n-channel MISFE that constitutes a memory cell of a DRAM or a peripheral circuit element.
It is formed in the same manufacturing process as the source region and drain region of T. n-type semiconductor region 3 which is the termination resistance element DR
Although it varies depending on the impurity concentration and the pn junction depth, it is formed with a resistance length of, for example, about 100 μm. Moreover, since the n-type semiconductor region 3, which is the terminating resistor element DR, is formed using the empty area around the semiconductor pellet, there is no substantial increase in the area occupied by the semiconductor pellet.

One end of the n-type semiconductor region 3, which is the termination resistance element DR, is connected to the wiring 7 through a connection hole 5 formed in the interlayer insulating film 4. This wiring 7 is connected to a wiring 10, which is a data input signal terminal (Din) 110, through a connection hole 9 formed in an interlayer insulating film 8. On the other hand, the other end of the n-type semiconductor region 3, which is the terminating resistance element DR, is connected to the wiring 10, which is the external terminal for power supply (Vtt) 112, with the wiring 7 interposed therebetween. Each of the wirings 7 and 10 is formed of, for example, an aluminum alloy film. Cu or Cu and Si are added to the aluminum alloy film. Although not limited to this structure, the n
An n-type semiconductor region 6 is interposed between one end and the other end of the type semiconductor region 3 and the wiring 7. n-type semiconductor region 6
is the MISF for memory cell selection of DRAM memory cells.
It is formed in order to prevent a short circuit between the complementary data line and the p-type semiconductor substrate 1 when the ET and the complementary data line (7) are connected.

The termination resistance element DR may be formed of a resistance element formed of a polycrystalline silicon film, but since the resistance value of the n-type semiconductor region 3 can be controlled more easily than that, in this embodiment, it is formed of an n-type semiconductor region 3. It is composed of a semiconductor region 3. Furthermore, the n-type semiconductor region 3 has a feature that its resistance value can be freely controlled with high precision by controlling the amount of impurity introduced. Further, the terminating resistance element DR may be formed in the same manufacturing process as the emitter region or the collector region, which are each operating region of the npn-type bibolar transistor, or in the same manufacturing process as the n-type well region.

In this way, E is connected to the input signal external terminal (Din) 110.
The semiconductor storage device 102 to which the CL interface circuit 111 is connected is used as one memory system on the mounting board 1.
In a memory board (electronic device) 100 in which a plurality of memory boards (electronic devices) are arranged regularly at 01, external terminals for input signals of the semiconductor memory device 102 (D in) 11
A terminating resistance element DR is built in parallel between 0 and the ECL interface circuit 111.

This termination resistance element DR is arranged on the main surface of the semiconductor substrate 1 of the semiconductor memory device 102. With this structure, the termination resistance element DR built into the semiconductor memory device 102 is formed within the area occupied by the p-type semiconductor substrate 1, and the area does not increase substantially, so that the mounting substrate of the memory board 100 The mounting density of the memory board 100 can be improved by an area corresponding to the area occupied by the termination resistor element DR externally attached to the mounting surface of the memory board 101. Furthermore, the number of components mounted on the mounting surface of the mounting board 101 of the memory board 100 can be reduced by an amount corresponding to the termination resistor element DR, and the probability of occurrence of mounting defects and electrical connection defects can be reduced. 100 electrical reliability can be improved.

Further, the terminating resistance element DR is inserted between the input signal external terminal (Din) 110 and the power supply external terminal (Vtt) 112 of the semiconductor storage device 102, as shown in FIG. 5 (equivalent circuit diagram). Good too. The input signal external terminal (Din) 110 of the semiconductor memory device 102 is actually connected to a lead via a bonding wire, and the semiconductor memory device 102 is mounted on the mounting surface of the mounting board 101 with the lead interposed. Therefore, the termination resistance element DR is arranged in parallel between the lead (external terminal or external pin) and the ECL interface circuit 111. Further, such arrangement of the termination resistance element DR is possible because the wiring 10 is used as the wiring 7 having a low resistance value.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, when address signals are individually input to the semiconductor memory device 102, the semiconductor memory device i! 102
external terminal for address signal and E connected in series with it.
A terminating resistance element may be built in in parallel with the CL interface circuit.

Further, the present invention can be applied to a memory board (electronic device) using an SRAM having an ECL interface circuit as a semiconductor memory device.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The packaging density of electronic devices can be improved.

Moreover, the electrical reliability of the electronic device can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of an ECL interface circuit built in a semiconductor memory device of the electronic device, and FIG. FIG. 4 is a plan view of a main part of the terminating resistance element built in the semiconductor memory device, FIG. 4 is a cross-sectional view of the main part of the terminating resistance element, and FIG. Equivalent circuit of the ECL interface circuit built into the device. FIG. 6 is a block diagram of a conventional electronic device. In the figure, 100...electronic device, 102...semiconductor storage device, 110, Din...external terminal for input signal, 111...ECL interface circuit, DL...
-Data input signal line, DR...terminal resistance element.

Claims (1)

[Scope of Claims] 1. In an electronic device in which a plurality of semiconductor memory devices each having an ECL interface circuit connected to an external terminal for an input signal are arranged regularly on a mounting board as one memory system, each of the semiconductor memory devices has an ECL interface circuit connected to an external terminal for input signals. 1. An electronic device comprising a terminal resistance element built in parallel between an input signal external terminal of the semiconductor memory device and an ECL interface circuit to which a data signal or an address signal input to the semiconductor memory device is applied. 2. The electronic device according to claim 1, wherein the termination resistance element is a diffusion layer resistance element formed on a main surface of a semiconductor substrate of the semiconductor memory device. 3. The electronic device according to claim 1 or 2, wherein a terminating resistor element for a clock-related signal commonly input to the semiconductor memory device is externally attached to the mounting board.