JPH0358472B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level detector used, for example, in an AGC circuit, in which the detection sensitivity is set by the reciprocal of temperature, eliminating the dependence of sensitivity on the detection level, and The purpose is to improve the sensitivity when

Traditionally, 8mm video tape recorders, etc.
The AGC circuit is configured as shown in Figure 1, in which 1 is a signal source formed by a video preamplifier, and 2 is a variable attenuation signal from signal source 1 that is input to a pair of input terminals a and b. and signal source 1
a buffer amplifier 2a that amplifies a signal of
b, and outputs the output signal of the amplifier 2a whose attenuation is controlled by the output variable circuit 2b, that is, the detected signal, from a pair of output terminals d and e.

3 is a level detector in which signals to be detected at output terminals d and e are input to a pair of input terminals f and g, and a level detector outputs a detection signal by detecting the level of the signals to be detected at input terminals f and g. A low-pass filter 3b is provided for smoothing the detection signal of the detector 3a' and outputting a control signal to the control terminal h.

Note that the control signal at the control terminal h is output to the control terminal c of the variable attenuation section 2. In addition, level detector 3
An AGC signal controlled to have a constant amplitude by AGC is output together with the detection signal from a', and the AGC signal is output from the output terminal i of the level detection section 3 to other circuit sections.

The details of the variable attenuation section 2 are constructed as shown in Fig. 2, in which Q1 and Q2 are a pair of NPN type transistors provided in the amplifier 2a, and a common emitter circuit for both transistors Q1 and Q2. is formed by the constant current source circuit T1, and the collectors of the transistors Q1 and Q2 are connected to the power supply terminal +B via collector resistors R1 and R2, respectively.
The signals at input terminals a and b are amplified by the differential amplification of both transistors Q1 and Q2, and the amplified signals are output from the collectors of both transistors Q1 and Q2 to output terminals d and e.

Q3 and Q4 are provided in the output variable circuit 2b.
A pair of NPN type transistors, with the collector and base of transistor Q3 being transistor Q1.
A variable current source circuit T2 is connected to the collector of the transistor Q4, and the collector and base of the transistor Q4 are connected to the collector of the transistor Q2, and the common emitter circuit of both transistors Q3 and Q4 is controlled based on the control signal of the control terminal c. It is formed by

Furthermore, the details of the level detector 3 are configured as shown in FIG. 3, and Q5 and Q6 are a pair of NPN type transistors forming a first differential amplifier circuit.
The bases of both transistors Q5 and Q6 are connected to input terminals f and g, respectively, and a common emitter circuit of both transistors Q5 and Q6 is formed by a constant current source circuit T3.

R3 and R4 are a series circuit of a collector resistor and a current limiting resistor provided in the collector circuit of the transistor Q5, that is, one collector circuit of the first differential amplifier circuit, and the collector resistor R3 is connected to the transistor Q5.
5, and a current limiting resistor R4 is connected to the power supply terminal +B. R5 and R6 are a series circuit of a collector resistor and a current limiting resistor provided in the collector circuit of the transistor Q6, that is, the other collector circuit of the first differential amplifier circuit, and the collector resistor R5 is connected to the collector of the transistor Q6,
A current limiting resistor R6 is connected to the power supply terminal +B.

Q7 and Q8 form a second differential amplifier circuit
They are a pair of NPN type transistors, and are connected to the power supply side from the connection point p of the base resistors R3 and R4 of the transistor Q7, that is, the collector resistor R3, and the base of the transistor Q8 is connected to the collector of the transistor Q6 and the collector resistor R5. connection point
p', that is, the collector resistor R5, is connected to the transistor side, and a common emitter circuit of both transistors Q7 and Q8 is formed by a constant current source circuit T4. R7 is the collector resistance of transistor Q8.

Q9 and Q10 form a third differential amplifier circuit
A pair of NPN type transistors, the base and collector of transistor Q9 are
The base and collector of the transistor Q10 are connected to the connection point of the resistors R5 and R6 and the power supply terminal +B, respectively, and the common emitter circuit of both transistors Q9 and Q10 is connected to the constant current source circuit T5. It is formed by

Q11 is a PNP type transistor whose base is connected to the collector of transistor Q8, and whose emitter is connected to power supply terminal +B.

C and R8 are a filter capacitor and a filter resistor forming the low-pass filter 3b, one end of the parallel circuit of the capacitor C and resistor R8 is connected to the collector of the transistor Q11 and the control terminal h, and the other end of the parallel circuit is grounded. ing.

Note that the output terminal i is connected to the collector of the transistor Q6, and the collector of the transistor Q7 is connected to the power supply terminal +B.

Also, resistors R3 and R5 have the same resistance value Rx,
Resistors R4 and R6 also have the same resistance value Ry.

Next, the operations shown in FIGS. 1 to 3 will be explained in conjunction with FIGS. 4 to 7.

The signal of signal source 1 is differentially amplified by both transistors Q1 and Q2 of buffer amplifier 2a, and the signal of signal source 1 is amplified between the collectors of both transistors Q1 and Q2, that is, the non-inverting output terminal and the inverting output terminal of amplifier 2a. A detected signal is generated.

On the other hand, due to the current change in the common emitter circuit of the variable output circuit 2b based on the control signal, the forward resistance value of the diode equivalently formed by the transistors Q3 and Q4 is variably controlled, and the change in the resistance value causes the detected signal to be The amplitude of is controlled.

Further, a first differential amplifier circuit formed by transistors Q5 and Q6 is driven by constant current source circuit T3, and a second differential amplifier circuit formed by transistors Q7 and Q8 and transistors Q9 and Q1 are driven by constant current source circuit T3.
The third differential amplifier circuit formed by 0 is driven by constant current source circuits T4 and T5 of the same current, respectively.

If the current flowing through the common emitter circuit of the first differential amplifier circuit is _I1 , then when the detected signal is not input to the input terminals f and g, the transistors Q5 and
Since the collector current of Q6 is I ₁ /2, the potential difference between the voltage Vp at the connection point p and the voltage Vp' at the connection point p' is
I ₁ Rx/2, and at this time, the base circuit of transistor Q8 is set to cutoff bias, so the operating point of transistor Q8 becomes point α on the operating curve of FIG. 4, and transistor Q8 shown in FIG. The collector current Ic of becomes 0, and conversely, the collector current Ic of the transistor Q becomes 0.
7 becomes the current I ₂ flowing through the common emitter circuit of the second differential amplifier circuit.

Note that the transistor Q7 of the second differential amplifier circuit and the transistor Q10 of the third differential amplifier circuit operate in the same manner, and the transistor Q8 and the transistor Q9 operate in the same manner.
works the same as .

Next, when the detected signal is input to the input terminals f and g, the transistors Q5 and Q6 operate symmetrically, and the voltage Vp' at the connection point p' changes due to the operation of the transistor Q6, and the base of the transistor Q8 changes. The circuit bias changes from the cutoff bias.

Then, the level of the signal to be detected becomes a predetermined detection level, and the operating point of transistor Q8 becomes α in FIG.
When transitioning from point to point β, transistor Q1
The bias of the base circuit of transistor Q11 decreases and transistor Q11 turns on for the first time, but at this time,
The voltage at the connection point p due to the operation of the transistor Q5
Vp changes as shown by the solid line l in FIG. 6, and the voltage Vp' at the connection point p' changes as shown by the solid line l' in FIG. 6 due to the operation of the transistor Q6.

Note that A in FIG. 6 indicates the signal amplitude (peak value) at the connection point p', and B indicates the signal amplitude (peak value) at the connection point p. Also, B is A {Ry/(Rx+Ry)}
It is indicated by.

That is, when the signal amplitude A satisfies the following equation (1), the operating point of the transistor Q8 is β in FIG.
The transistor Q11 is turned on.

(A/2(1+Ry/Rx+Ry)+NKT/q=I ₁ Rx/2) ...(1) formula In the formula, N is a constant, K is Boltzmann's constant,
T represents absolute temperature, and q represents electric capacity of unit charge.

The collector current Ic of transistor Q8 when signal amplitude A satisfies equation (1) is expressed by equation (2) below. Resistance value is set.

Ic=I ₂ /(1+e×pN)... (2) Then, the level detector 3a' detects the signal to be detected based on the voltage of the collector circuit of the transistor Q8, that is, the voltage Vp' at the connection point p'. Q11 is turned on, and the detection signal consisting of the collector current of transistor Q11 is smoothed by the low-pass filter 3b.
A control signal is output from the variable current source circuit T2.

Further, the current of the variable current source circuit T2 is controlled by the control signal so that the voltage Vp' at the connection point p' becomes a voltage with a constant amplitude, that is, the base circuit of the transistor Q8 becomes a cutoff bias, The AGC signal consisting of the voltage Vp' at the connection point p' is controlled to a signal with a constant amplitude before detection.

That is, when the amplitude of the signal to be detected increases and the bias of the base circuit of transistor Q8 changes from the cutoff bias, the level detector 3a' detects
For example, by adjusting and setting the voltage Vp' at the connection point p' with respect to the detected signal, the level of the detected signal when changing from the cutoff bias, that is, the detector level, can be adjusted. Can be set variably.

By the way, by transforming equation (1), we get the following (3)
We can obtain the formula.

A=I ₁ Rx-2 (NKT/q)/(1+Ry/Rx+Ry)...(3)
Equation Furthermore, since A>0 in equation (3), the following equation (4) can be obtained.

I ₁ Rx>2(NKT/q...Equation (4) And the sensitivity of the level detector 3a' is based on Equation (3) as shown in Equation (5) below. Note that Z in Equation (5) is q /(2NK) constant.

(d/dTA/A)=1/(T-I ₁ RxZ)...Equation (5) And the relationship between sensitivity (d/dTA/A) and voltage (I ₁ Ry) in Equation (5) is 7th based on the value of
A graph is displayed as shown in the figure.

Note that the solid lines t1, t2, and t3 in FIG. 7 indicate the temperature T.
is T1, T2, T3, respectively, and T1
<T2<T3. Also, the broken line v is β in Fig. 4.
The broken line v' indicates when the point is set as the detection level, and the broken line v' indicates when the transistor Q11 is set to turn on for the first time when the collector current Ic is larger than the current at point β, that is, the detection level is set as the point β in Fig. 4. Indicates when set higher. Furthermore, in FIG. 7, when the absolute value of (d/dTA/A) is 0, the sensitivity is highest.

As is clear from Fig. 7, for example, if the detection level point is set at point β of the broken line v, the sensitivity will shift from point S1 to point S2 to point S3 and decrease due to the rise in temperature, and the detection level When moving from the point of the broken line v' to the point β of the broken line v, the sensitivity decreases moving from the point S1' to the point S1, or from the point S2' to the point S2, or from the point S3' to the point S3.

In other words, the sensitivity of level detector 3a' in Fig. 3 is
As shown in equation (5), 1/(T-I ₁ Rx/Z) < 0, so the sensitivity depends on the temperature and detection level,
Sensitivity deteriorates as the temperature rises, and the sensitivity deteriorates as the detection level of the detected signal is lowered.

On the other hand, in order to make 8mm video tape recorders portable, it is desirable to make them smaller and lighter.In this case, the power supply voltage is set low and the amplitude of the detected signal and AGC signal is reduced to reduce power consumption. There is a need to.

However, as mentioned above, the sensitivity of the level detector 3a' deteriorates as the level detector decreases, so the amplitude of the detected signal is constrained by the sensitivity of the level detector 3a'. There is a limit to reducing power consumption by making the device smaller.

The present invention has been made with the above points in mind, and includes a first differential amplifier circuit into which a detected signal is input, and one base circuit in one collector circuit of the first differential amplifier circuit. a second differential amplifier circuit in which the other base circuit is connected to the other collector circuit of the first differential amplifier circuit; In a level detector for obtaining a detection signal, the one base circuit is connected to the power source side of the collector resistor of the one collector circuit, and the other base circuit is connected to the transistor side of the collector resistor of the other collector circuit. the other base circuit is held at a cutoff bias when the detected signal is not input;
A constant current transistor whose collector and emitter are connected in series to a common emitter circuit of a differential amplifier circuit, a control transistor whose collector and base are connected to the base of the transistor and a constant current source circuit, and an emitter of the transistor. and a diode circuit that is forward biased by a current, and the control transistor and the diode circuit control the current of the common emitter circuit to a current of a first-order coefficient term of temperature. It is something to do.

Therefore, according to the level detector of the present invention, since the current of the common emitter circuit of the first differential amplifier circuit is controlled to the current of the first-order coefficient term of temperature,
The sensitivity of the level detector depends only on the inverse of the temperature,
This eliminates the dependence of sensitivity on the detection level, making it possible to measure sensitivity improvement when the detection level is low.

Next, this invention will be explained in detail with reference to FIG. 8 showing one embodiment thereof.

In the same figure, the same symbols as in FIG. 3 indicate the same or equivalent parts, 3a is a level detector provided in place of level detector 3a' in FIG. 3, and Q
12 is an NPN type constant current transistor;
The collector is connected to the emitter of transistors Q5 and Q6, and the emitter is connected to the emitter resistor R.
It is grounded via 8.

Q13 is an NPN type control transistor,
The collector and base are connected to the base of transistor Q12 and constant current source circuit T6. Q1
4 is an NPN type transistor forming a diode circuit, the collector and base of which are connected to the emitter of transistor Q13, and the emitter is grounded.

The voltage between the base and emitter of transistor Q12 is controlled by the voltage between the base and emitter of transistor Q13, and the voltage drop across resistor R8 is controlled by the voltage between base and emitter of transistor Q14.

By the way, transistors Q12, Q13, Q14
The voltage between the base and the emitter of each of the transistors Q12 to Q14 is equal to the voltage Vbe, and since the voltage between the base and the emitter of each transistor Q12 to Q14 becomes a voltage with so-called diode characteristics, the voltage Vbe is expressed by the following equation (6).

Vbe=KT/qlogeIo/Is...Equation (6) Note that Io is the current between the base and emitter, and Is is the saturation current.

Therefore, the current _I1 flowing through the common emitter circuit of the first differential amplifier circuit is the base of the transistor Q14,
It is controlled by the emitter voltage, and then becomes a current of the first-order coefficient term of the absolute temperature T, as shown in equation (7).
Note that Rz is the resistance value of the resistor R8.

I ₁ =Vbe/Rz=KT/qRzlogeIo/Is...Equation (7) And by substituting the current I ₁ in Equation (7) into Equation (3), the following Equation (8) is obtained.

A={(KRx/qRzlogeI ₀ /Is)-2(NK/q)}T/
(1+Ry/Rx+Ry)...Equation (8) In other words, in the case of FIG. 8, the operating point of transistor Q8 shifts to point β in FIG.
The signal amplitude A at the connection point p' for turning 11 on is expressed by equation (8).

Then, the sensitivity (d/dTA/ A) is determined by the following equation (9).

(d/dTA/A)=1/T...Equation (9) Therefore, the sensitivity of the level detector 3a depends only on the reciprocal of temperature, and the detection level dependence of sensitivity is eliminated, and when the detection level is low The sensitivity is improved compared to the case of FIG. 3, and it is possible to improve the sensitivity when the detection level is low.

In addition, while the sensitivity in equation (5) is a negative value, the sensitivity in equation (9) is a positive value, and furthermore, the temperature coefficient of transistor Q11 when it is in the on state is also a positive value, so the detection can be stabilized.

Since the sensitivity does not deteriorate even if the level of the detected signal is lowered, a detected signal with a smaller amplitude than in the case of FIG. 3 is detected by the level detector 3a.
AGC signals can be output, and an 8mm video tape recorder or the like can be made significantly smaller and lighter than the case shown in Fig. 3, making it very effective when applied to equipment that aims to be smaller and lighter.

In the above embodiment, the level detector 3a includes a first differential amplifier circuit including transistors Q5 and Q6, a second differential amplifier circuit including transistors Q7 and Q8, and a third differential amplifier circuit including transistors Q9 and Q10. However, basically, the same effect can be obtained even if only the first and second differential amplifier circuits are provided.

Further, although the diode circuit is formed by the transistor Q14, the same effect can be obtained by forming it by a diode, and furthermore, the diode circuit may be provided with a plurality of transistors or a series circuit of diodes.

Further, in the above embodiment, in order to apply to a CGC circuit, the detection signal is output from the transistor Q11 to the low-pass filter 3b, and the AGC signal is taken out from the collector of the transistor Q6. When applied to a circuit that detects the level of output signals of various sensors, it is sufficient to output only the detection signal.

Further, in the above embodiment, the transistor Q11 is connected to the collector circuit of the transistor Q8, that is, the other collector circuit of the second differential amplifier circuit to obtain the detection signal. The detection signal may be obtained by connecting the transistor Q11 to one collector circuit of the amplifier circuit, or the collector voltage of the transistor Q8 or the transistor Q7 may be directly used as the detection signal.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the AGC circuit, Fig. 2 is a wiring diagram of the variable attenuation section of Fig. 1, Fig. 3 is a wiring diagram of the level detection section, and Fig. 4 is a wiring diagram of the transistor Q8 of Fig. 3.
5 is a wiring diagram of the second differential amplifier circuit of FIG. 3, and FIG. 6 is a diagram of the transistor Q of FIG. 3.
7. A waveform diagram of the signal amplitude input to the base of Q8, Figure 7 is a sensitivity curve diagram of the level detector of Figure 3, and Figure 8 is a wiring diagram of one embodiment of the level detector of the present invention. . 3a... Level detector, Q5, Q6... Transistors forming the first differential amplifier circuit, Q7, Q8
...transistor forming the second differential amplifier circuit,
Q12... Constant current transistor, Q13...
Control transistor, Q14...transistor forming a diode circuit, R3, R5...collector resistor, R8...emitter resistor, T6...constant current source circuit.

Claims (1)

[Claims] 1 A first differential amplifier circuit into which the signal to be detected is input; one base circuit is connected to one collector circuit of the first differential amplifier circuit; and one base circuit is connected to the other collector circuit of the first differential amplifier circuit. a second differential amplifier circuit connected to the other base circuit;
A level detector that obtains a detection signal from one or the other collector circuit of the second differential amplifier circuit,
Connecting the one base circuit to a power source side of the collector resistor of the one collector circuit,
the other base circuit is connected to the transistor side of the collector resistor of the other collector circuit, the other base circuit is held at a cutoff bias when the detected signal is not input, and the first differential amplifier circuit A constant current transistor whose collector and emitter are connected in series to a common emitter circuit; a control transistor whose collector and base are connected to the base of the transistor and a constant current source circuit; 1. A level detector comprising a biased diode circuit, wherein the control transistor and the diode circuit control the current of the common emitter circuit to a current of a linear coefficient term of temperature.