JPH0358523A - Echo canceller test equipment - Google Patents

Abstract

PURPOSE:To reduce the scale of the equipment by using an output of a resistance attenuator via a switch as an output as it is when an analog signal is outputted and using an output of an A/D converter via a switch as an output when a digital signal is outputted. CONSTITUTION:When an analog input signal comes, an A/D converter 60 is used to convert it into a digital signal offering ease of delay, the signal is retarded digitally by a digital delay circuit 62 and the retarded signal is converted into an analog signal by a D/A converter 63. The the output of the D/A converter 63 is attenuated by an analog attenuator 64 and the result is outputted as an analog signal. When an input digital signal comes, the signal is inputted as it is to the digital delay circuit 62, where the signal is delayed as required and the signal is converted into an analog signal by the succeeding D/A converter 63, attenuated by the analog attenuator 64 offering ease of attenuation and the signal is converted into a digital signal by the succeeding A/D converter 66 and the digital signal is outputted. Thus, the circuit scale is decreased.

Description

[Detailed Description of the Invention] [Il! [Required] The present invention relates to an echo canceller testing device for testing the function of an echo canceller, and its F1 objective is to provide a small-scale echo canceller testing device, and when an input signal is an analog signal, the analog signal is An A/D converter that converts to a digital signal, and a switch that selects the output of the A/D converter if the input signal is an analog signal, or selects the digital signal if the input signal is a digital signal. a digital delay circuit that receives the output of the switch and digitally delays it according to an external setting value; a D/A converter that converts the output of the digital delay circuit into an analog signal;
an analog attenuator that attenuates the output of the /A converter in an analog manner, a switch that branches the output of the analog attenuator into two directions, and an A/D converter that converts the output of the analog attenuator into a digital signal. When the output is an analog signal, the output of the resistor attenuator is output as is through the switch, and when the output is a digital signal, the output of the A/D converter is output through the switch. Configure the output to be that output.

[Industrial Application Field] The present invention relates to an echo canceller testing device for testing the function of an echo canceller.

[Prior Art] Fig. 4 is a conceptual diagram of a conventional network system. ] is a pBX (++'t internal exchange), to which multiple telephones 2 are connected. 3 is a special division multiplexing/demultiplexing device (TDM) connected to the PBXI and multiplexing and demultiplexing multiple channel signals. The TDM is connected to another TDM 5 via a digital same line 4. 6 is a PBX connected to the TDM 5, and a plurality of telephones 7 are connected thereto.

In the system configured as described above, when the telephone 2 makes a call, the signal enters the TDM 3, is multiplexed, and is sent to the TDM 5 via the digital outlet line 4.

TDM5 separates the input signal and sends it to PBX6.

The PBX 6 connects a telephone 7 for each input channel.
Connect with. In this way, telephone 2 and telephone 7 are connected.

The same applies when connecting from telephone 7 to telephone 2.

In such a switching system, since the digital line 4 has 4 wires and the telephone 2.7 has 2 wires, it is necessary to convert between 4 wires and 2 wires. This 4-wire/2-wire conversion function is PBXI,
It will be installed within 6. FIG. 5 is a block diagram showing an example of the structure of a 4-line 72-line conversion circuit. A transformer 11 is connected in series to the receiving line 10, and the secondary side of the transformer 11 is connected to the telephone set 1.
2 is connected. Here, the line connected to the telephone 12 is of a two-wire type. A balance circuit 13 for impedance matching is connected to the other end of these two wires. 14 is a transmission line connected to the two wires on the telephone 12 side.

In a circuit configured in this way, the received signal is
The signal flows through the receiving line 10. This audio current is the transformer 11
The audio signal is transmitted to the secondary side of the secondary side. On the secondary side of the transformer, the signal induced in the coil enters the telephone 12 as a voice signal. Here, if the impedances of the balance circuit 13 and the telephone set 12 are equal, the received signal will not leak to the transmission line 14. However, in reality, the impedances of the balance circuit 13 and the telephone 12 are never equal, and the received signal is transmitted to the telephone 12.
leaks from the side to the transmission line 14 as shown in the figure. This leaked signal is called an echo, and the caller's own voice is heard on the caller's phone with a slight delay.

An echo canceller is used to cancel such echoes. This echo canceller cancels leaked echoes and prevents them from being superimposed on the transmission line. This echo canceller is provided in the TDMs 3 and 5 in FIG. FIG. 6 is a diagram showing an example of the internal configuration of the TDM. Signals coming from the PBX enter a line set (LS) 20, and the outputs of the line set 20 are multiplexed by a time switch 21 and output. The output multiplexed signal is sent to the digital line 4.
Transmitted by On the other hand, the multiplexed signal coming from the digital same line 4 lasts for one hour. Enters Sochi 22, is separated into channels, and is connected to a PBX via line stations So 1 and 23.
sent to. Here, 24 is an echo canceller installed between the line sets 20 and 23, and is designed to cancel echoes that go around from the receiving side to the transmitting side.

Figure 7. FIG. 8 is a diagram showing a test port of the echo canceller. FIG. 7 shows a test circuit for an analog echo canceller, and FIG. 8 shows a test circuit for a digital echo canceller. The human power Rln is outputted through a codec 30, and a test device consisting of an analog delay path 31 and an analog attenuator 32 is connected to the output of the codec 30. The outputs of these test devices are manually input to the codec 30. As a result, an echo flows into the codec 30 in a pseudo manner. This echo is generated by delaying the output of the codec 30 by a delay circuit 31, and then by an attenuator 32.
The amplitude is attenuated by the codec 30 as an echo.
give to

The output of the codec 30 enters an echo canceller 33. The input signal RID enters the echo canceller 33 as it is, and is internally applied to the echo as a signal for canceling the echo. Then, the output S of the echo canceller 33 6. , by measuring with a level meter, the degree of echo attenuation (dB) is determined.

The example in FIG. 8 shows an example of a digital test device. That is, the input signal Rl, . is input into a digital delay circuit 34 and delayed, and then input into an attenuator 35 where it is attenuated. A pseudo echo signal from the output of the attenuator 35 enters the echo canceller 36 . The echo canceller 3
6 inputs the input signal Rln to the human input, and applies Rlfi to the pseudo echo signal to cancel the echo. Then, the degree of attenuation of the echo of the echo canceller 36 can be measured from the output S eul of the echo canceller 36 .

[Problems to be Solved by the Invention] As described above, the echo canceller test device is realized by a series circuit of a delay circuit and an attenuator. In general, delay circuits are easier to implement in a digital format than in an analog format, and attenuation circuits are easier to implement in an analog format than in a digital format. When implementing a delay circuit using an analog method, a delay line 40 as shown in FIG. 9 is required. This delay line 4
0 has taps at predetermined distance intervals, and by arbitrarily changing the positions of these taps with a switch 41, a necessary delay time can be set. This type of delay line requires a large volume, which increases the scale of the test equipment.

On the other hand, if the delay circuit is implemented digitally, circuits such as those shown in FIGS. 10 and 11 can be used. The same path shown in FIG. 10 is an example using a FIFO memory, and FIG. 11 is an example using a dual port RAM. In Figure 10, the write data is FI
When data is input to the FO memory 42, it is sequentially written therein by a clock. When reading the written data,
It is as follows.

A counter 43 counts clocks, and its count output A is input to a comparator 44. On the other hand, the set value B is input to the comparator 44, and the comparator 44 rises to "1" when A≧B.

At this rising edge, the gate 45 opens and the read clock is output. This read clock causes the sequentially written data to be output as read data. Here, the delay time is determined by the comparator 44! It can be set arbitrarily by changing the set value. That is, the larger the set value B is, the larger the delay interval becomes.

In FIG. 11, write data is manually input to the dual baud RAM 46, and the counter 4 that counts the clock
It is written sequentially by the output of 7.

On the other hand, the counter output A and the set value B are stored in the attenuator 48, and the attenuator 48 performs the calculation of (A-B).

The output of the attenuator 48 is input to the dual port RAM 46 as a read clock, and read data delayed according to the output of the attenuator 48 is sequentially output. As explained above, Figure 10. In either case of FIG. 11, the digital delay circuit can be realized with a simple configuration.

FIG. 12 is a diagram showing an example of the configuration of a digital attenuation circuit. The input signal enters a nonlinear/linear conversion circuit 50 and is converted into a linear signal.

Generally, transmission signals such as audio are compressed using logarithmic compression characteristics as shown in FIG. In other words, the compression ratio is reduced to increase the resolution in areas where human power is small, and the compression ratio is increased to lower resolution in areas where human power is large, making it easier to hear even at low volumes. A signal (PCM code signal) having such nonlinear characteristics is returned to linearity by a four-way nonlinear/linear conversion 50.

The output of the nonlinear/linear conversion circuit 50 is input to one side of the digital multiplier 51. The digital multiplier 5
The output of the set value/attenuation constant conversion circuit 52 is input to the other input terminal 1. When a set value is entered manually, the set value/attenuation constant conversion circuit 52 converts it into an attenuation constant according to the set value and supplies it to the digital multiplier 51 . The digital multiplier 51 multiplies the output of the nonlinear/linear conversion circuit 50 and the output of the set value/attenuation constant conversion circuit 52. In other words, the digital method uses a complicated procedure to attenuate the input signal by multiplying it by a decay constant of 1 or less. The output of the digital multiplier 51 enters a linear/nonlinear conversion circuit 53, where it is converted again into a nonlinear signal and then output.

On the other hand, analog attenuation circuits can attenuate signals by simply dividing the input signal using a resistor voltage divider 47, as shown in FIG. 1
It is 1.

As mentioned above, when an echo canceller test device is implemented using an analog method, the problem is the large scale of the delay channel, and when it is implemented using a digital method, the complexity of the structure of the attenuation channel becomes a problem. It became.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an echo canceller test device that can reduce the circuit scale.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In the figure,
60 is an A/D converter that converts the analog signal into a digital signal when the input signal is an analog signal;
1 is a switch that selects the output of the A/D converter 60 when the input signal is an analog signal, and selects the digital signal when the input signal is a digital signal;
62 is a four-way digital delay circuit that receives the output of the switch 61 and digitally delays it in accordance with an external setting value.

63 is a D/A converter that converts the output of the digital delay circuit 62 into an analog signal, 64 is an analog attenuator that attenuates the output of the D/A converter 63 in an analog manner, and 65 is the output of the analog attenuator 64. A switch 66 is an A/D converter that converts the output of the analog attenuator 64 into a digital signal.

[Function] If the input is an analog signal, the A/D converter 6
0 into a digital signal that is easy to delay, the digital delay circuit 62 digitally delays the signal, and the D/A converter 63 converts this delayed signal into an analog signal. Then, the output of the D/A converter 63 is attenuated by an analog attenuator 64, and then output as an analog signal.

If the manual input is digital, the digital delay circuit 62 is manually input to perform a predetermined delay, and then continue < D
/A converter 63 converts it into an analog signal and attenuates it with an easy-to-attenuate analog attenuator 64.
is converted back into a digital signal and output as a digital signal.

In this way, according to the present invention, by using an analog-digital mixed method in which delay, which is difficult to achieve with analog, is achieved digitally, and attenuation, which is difficult to achieve digitally, is achieved in analog, it is possible to achieve both analog and digital methods. It can also be used to test echo cancellers. Furthermore, the circuit scale is reduced and a highly reliable test system can be realized.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. In the figure, 60 is a PCM coder as an A/D converter, 63 is a PCM decoder as a D/A converter, 6
6 is a PCM coder as an A/D converter, and 64 is a resistance attenuator as an analog attenuator. The digital delay gate 62 is composed of a FIFO memory 62a and a control port 62b for controlling the FIFO memory 62a. The operation of the circuit configured as described above will be explained as follows.

First, the case where the input is an analog signal will be explained. Input No. 13 enters a PCM coder 60 and is converted into a digital PCM code signal.

At this time, the switch 61 is connected to the PCM coder 60 side, and the converted PCM signal enters the FIFO memory 62a via the switch 61.

On the other hand, the control circuit 62b generates a write 1 signal (write signal) from the internal clock and supplies it to the FIFO memory 62a. As a result, input data is sequentially written into the FIFO memory 62a.

On the other hand, the delay setting value is manually entered in the control block 62b. The control path 62b generates a read signal according to a manually set value and supplies it to the FIFO memory 62a. As a result, the written data is read by the read signal which is output later than the write 1 signal.

FIG. 3 is an explanatory diagram of the operation of the digital delay circuit. FI
Data is written into the FO memory 62a at the address indicated by the write pointer, as shown in the figure. D in the figure. ,D
n-1+...I), -8 indicates written data. The written data is read out as read data from the address indicated by the read pointer. This read pointer must always point at least one address after the write pointer.

Here, the difference (depth) between the write pointer and read pointer
can be controlled by the control circuit 62b to adjust the delay time. For example, write/read frequency is 8KH
When data is read from Dn-1 at time z, the delay time is O.z. '5ms, and when data is read from D7-8, the delay time is 1. It becomes m s.

Data read from the FIFO memory 62a enters the PCM decoder 63 and is converted into an analog signal. This analog signal is attenuated in amplitude by the required amount by resistive attenuator 64. The signal whose amplitude has been attenuated is output as an analog signal via a switch 65 connected to the analog side.

Next, a case where the human power is a digital signal will be explained. In this case, the switch 61 is connected to the digital human power side. The digital signal input to the FIFO memory 62a is delayed according to a set value by a control signal manually input from the control circuit 62b, and then read out from the FIFO memory 62a.

The read data is converted into an analog signal by the PCM decoder 63.

The converted analog signal then enters a resistive attenuator 64 where its amplitude is attenuated. The resistive attenuator 64 has a configuration as shown in FIG. 14, and is composed only of a resistive voltage divider. The attenuated analog signal enters the PCM coder 66 via a switch 65 connected to the PCM coder 66 side, is converted into an original digital signal, and is then output as a digital signal. As described above, according to the present invention, delay, which is difficult to achieve with analog, can be achieved digitally, and attenuation, which is difficult to achieve digitally, can be achieved in analog, thereby converting analog signals. We can provide echo canceller test equipment that can handle both digital signals.

In the above-mentioned same path, the PCM coders 60 and 66 can use, for example, a PCM code LSI, and furthermore, by using them in a time-sharing manner, the PCM coders 60 and 66 can be used in common. Further, the PCM decoder 63 can also be implemented as an LSI, and can be incorporated into the same package as the PCM coders 60 and 66, for example.

[Effects of the Invention] As explained in detail above, according to the present invention, by digitally realizing delays that are difficult to achieve with analog, and realizing attenuation that is difficult to achieve digitally, it is possible to achieve both analog and digital signals. It is possible to provide an echo canceller test device that can handle this, and the scale of the device can also be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a structural block diagram showing an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of a digital delay circuit, and Fig. 4 is a diagram of a conventional network system. 1. Conceptual diagram. Figure 5 is a block diagram showing an example of the configuration of a 4-wire/2-wire conversion port. Figure 6 is a diagram showing an example of the internal configuration of a TDM. Figure 7 is a diagram of an analog echo canceller. Figure 8 is a diagram showing a test circuit for a digital echo canceller. Figure 9 is a diagram showing a delay parallel path using an analog system.
figure. Figure 11 is a diagram showing a delay circuit using a digital system, Figure 12 is a diagram showing an example of the configuration of an attenuation path using a digital system, Figure 13 is a diagram showing compression characteristics of a transmission signal, and Figure 14 is a diagram using an analog system. It is a figure which shows the example of a structure of an attenuation same path.

Claims (1)

[Claims] A device that receives an input signal, applies a predetermined delay and a predetermined amplitude attenuation, outputs a pseudo echo signal, and supplies it to an echo canceller, and when the input signal is an analog signal, the analog An A/D converter (60) that converts the signal into a digital signal; is the switch that selects the digital signal (
61), and a digital delay circuit (61) that digitally delays the output of the switch (61) according to an external setting value.
2), a D/A converter (63) that converts the output of the digital delay circuit (62) into an analog signal, and a D/A converter (63) that converts the output of the digital delay circuit (62) into an analog signal.
3) An analog attenuator (
64), a switch (65) that branches the output of the analog attenuator (64) into two directions, and an A/D converter (66) that converts the output of the analog attenuator (64) into a digital signal. When the output is an analog signal, the switch (6
5) to output the output of the resistive attenuator (64) as it is, and if the output is to be converted into a digital signal, the output of the A/D converter (66) is connected to the output of the A/D converter (66) via the switch (65). An echo canceller test device configured to perform