JPH0358546A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To attain circuit integration by providing an exclusive OR element receiving a couple of data outputs of a data flip-flop, and a final stage exclusive OR element integrating outputs of the exclusive OR elements and sending a signal to a loop filter. CONSTITUTION:The circuit is provided with plural parallel data flip-flops 11-14 receiving a polyphase PSK modulated wave signal and a clock signal, and phase shifters 21-23 whose phase is deviated by pi/n each with respect to a clock signal input line. Then a signal is sent to a loop filter from a final stage exclusive OR element 40 through exclusive OR elements 31, 32 receiving outputs of the flip-flops 11-14 in pairs. Thus, the phase shifters act like shift registers without use of a filter element comprising of capacitors and resistors, adder/ subtractor circuits and a multiplier element/and the circuit is integrated entirely.

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention is applicable to carrier wave regeneration during demodulation using a polyphase phase shift key ink (PSK) transmission method, and is used as a phase difference detector in a phase synchronized circuit. Regarding the phase comparator.

``Prior Art'' Conventionally, the Costas loop method using baseband processing, the inverse modulation method, and the N-broadcast method are known as carrier wave regeneration methods for a demodulator that should be provided on the receiving side of a communication line using a polyphase PSK method. It uses analog elements and has a complex circuit configuration, making it difficult to meet the demands of digitalization.

For example, FIG. 4 shows an example of a circuit that demodulates a four-phase PSK signal using a Costas loop as a phase comparison means. To explain the phase difference detector 100, first, the modulated wave f, = Asia ( ωt +nyr /
2) VCOIO output frequency f ,==sin (
ωt+θ), frequency f via phase shifter, = cos(
ωt + θ), θ is a steady phase difference, and n = 4, then the multiplication result by multiplier l is
2=A/2sin (nyt/2-θ),
Multiplier 2 calculates f 3 = A/ 2 cos ( n
π/2−θ) is obtained.

? The above f! and the multiplier 30 multiplication result by r3 is f
4 - = A2/8sin (II π-2θ), addition n
s s vc -%"lt f2 and f3 above and K.
The addition result is In −=A/2sin (n
rr /2-θ) +A/2cos(nπ/2-θ
), and the subtraction antagonist of the above f2 and r3 in the subtractor 6 (is fo = A/2 sin (nπ/2-θ)-A
/2cos(nπ/2-θ) and 4c, multiplier 4
The multiplication result f + o - A of the above f, and f, which is pressed.
2/4cos((1π-2θ) is obtained, and the above r,
and the multiplier 5 is given Eri f, -A'/64sin (2nπ
−4θ) is obtained.

Here, the value of sin (2 nπ-4θ) of the above f is obtained as the value of r]. In other words, the input phase change is nO,
], 2. 3 Regardless of &, the output is determined by the phase error 4θ, and the error input voltage to CO becomes constant.

This means that the carrier wave can be regenerated when the system is in a stable quasi-state, but the above Costas group has L P
2 F, 1 each of adder and subtractor, and 5 multipliers are required, and since the adder and subtracter mentioned above are directly connected to DC, they are only affected by the offset voltage and 7: C < , L P F"
, addition, subtraction, and multipliers, so there are obstacles and difficulties, such as the fact that the circuit structure cannot be constructed using only general-purpose ICs.

``Problems to be Solved by the Invention'' Therefore, the present invention solves the problem when demodulating a multiphase PSK signal. 1',
-LPF, add-on, and
The purpose is to eliminate the subtractor and the like to create a circuit structure that exhibits the advantage of miniaturization in proportion to multi-phase design.

``Means for Solving the Problems'' Thus, the present invention provides a plurality of parallel data flip-flops that receive a polyphase PSK modulated wave signal and a clock signal, and a π/ A phase shifter having a phase shift of n is provided, and a signal is sent from the final stage exclusive OR element to the loop filter via an exclusive OR element into which the outputs of the flip-flop are input as a pair. It is.

An embodiment of the present invention will be described below with reference to FIG. 1 and FIGS. 2 and 3.

"Example" Figure 1 is an example of handling a 4-phase PSK modulated wave signal.
7rl is an input line terminal for the polyphase PSK modulated wave, `r2 is an input line terminal for the clock signal, and an output terminal for the T3 loop filter. 11.12.13.14 is a data Frisobuflow knob with 2 signal human power and 1 signal output.
21 22. 23 is a phase shifter for shifting the phase by π/0, 31.32 is an exclusive OR element into which the outputs of each of the Flinop flops are input as a one-to-one pair;
40 is a final stage exclusive OR element which inputs the output of the exclusive OR element.

The operation of such a structure will be explained below. Here, the data flip 7 flop maintains the state of the data at the rising edge of the clock σ) until the next clock σ) rises.

Considering the phase comparison function for the data input D and clock input and Q output of the data flip 7 lop, the phase difference Δφ of the clock input with respect to the data input is negative, that is, Δφ<0, and the two input signals are If the duty ratio is 50% at the same frequency, the relationship between Δφ and Q will be in the following two states. That is, (a) When 1π〈△φ＜0, Q=1, that is, ゜H” level (mouth), and 0〈△φ〈π, L Q=o, that is, ゜L” level, and in the range of Δφθ Corresponding Q output VCL, 2
The phase of two inputs can be determined. And that σ)
The period is 2π.

Output line a of each of the 7 flip-flops (FF) in Figure 1
The waveforms appearing in , b, c, and dK correspond to (1), (I), (C), and (D) in Figure 2, and are the waveforms of output lines e and f of exclusive OR elements 31 and 32. is Fig. 3←℃,
ω). And the final stage exclusive OR element 4
The output line gσ waveform of '0' becomes the waveform shown in FIG.

The characteristics of the phase comparator based on one data flip tip are as shown in Figures 2 to (D). (C) ,
(D) has a phase shift of π/4, 2π/4, and 3π/4. Therefore, Fig. 2 (1) ~ (The mouth has a period of 2π and the husband is π/4
It has a phase difference of

Next, the exclusive OR element 31 takes the exclusive OR of the outputs a and b of I':E11 and 12, and inputs a
, b and the output e are as shown in the table below. Note that the logic of the output f of 32 for the c and d inputs is also similar.

From the above, the exclusive OR element (31”l, (32
The graph of the output waveform of ) has two outputs with a period of π and a phase difference of π/2, as shown in FIG. 3 (6) and (b).

For example, the phase comparator Q required by 4 P S KKk
) characteristic is that it has a period π/2, so it is sufficient to take the exclusive OR of 31.32 above in the exclusive logic element 40 at the final stage, which is shown in Fig. 3 (q). It is shown.

"Effect" Therefore, according to the phase comparator of the present invention, since the data Q) phase change is nπ/2 during demodulation of the polyphase PSK wave, the carrier wave recovery phase lock loop can be maintained. This can be realized using a simple circuit structure that allows the same level of output to be obtained even if the above nπ/2 phase change occurs, and it consists of a filter element consisting of capacitor C resistors, an addition/subtraction circuit, and a multiplication element. By substituting a phase shifter for a shift register instead of using a phase shifter, it is possible to integrate the entire structure into ICs, and the main effect becomes more pronounced as the number of phases increases.

[Brief explanation of drawings]

Figure 1 is a wiring diagram of the phase comparator circuit of the present invention, Figure 2 (A)
-42 is an output graph of the data flip-flop shown in FIG. 1, FIG. 3 is an output graph of the exclusive OR element shown in FIG. 1, and FIG. 4 is a circuit configuration diagram of a conventional 9-phase comparator. T, ... Input line terminal of polyphase PSK modulated wave, T,
．． ．． ．． Input line terminal for clock signal, T3 . . . Output terminal 21 of phase comparator. 22. 23... Phase shifter, 11, 12, 13, 14... Data flip-flop, 31, 32. 40...Exclusive OR element.

Claims (1)

[Claims] In the phase comparator of the phase synchronization circuit that regenerates carrier waves during multiphase PSK demodulation, n data flip-flops (n = 2^P, P is a positive integer not including 0), m (=n-1) phase shifters that shift the phase of the input line of the clock signal by π/n, and the data output of the data flip-flop are input as a pair. and a final-stage exclusive OR element that integrates the outputs of the exclusive OR elements and sends a signal to a loop filter. A phase comparator circuit that regenerates carrier waves.