JPH0358546B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention generally relates to a technique for using a non-element part of an LSI semiconductor device as a capacitor, and particularly to a technique that is effective when applied to a master slice type semiconductor device.

[Background Art] In order to increase the switching speed of the internal gates of an LSI (large scale integrated circuit) semiconductor device, it is conceivable to add a speed-up capacitor as shown in FIG. In the figure, reference numeral 1 indicates a speed-up capacitor, and the speed-up capacitor 1 is connected in parallel to the emitter resistor 3 of the input gate transistor 2. A logic signal obtained from the collector resistor 4 of the input gate transistor 2 is taken out as an output signal via an output transistor 5 and a load resistor 6 connected to its emitter. In order to increase the switching speed of the NTL (non-threshold transistor logic) having such a configuration to a certain level, a speed-up capacitor 1 is required.

By the way, in a master slice type LSI semiconductor device, for example, in an LSI semiconductor device having four 3-input internal gates 7 as shown in FIG. 2, when forming a 6-input internal gate, for example, two One 6-input internal gate is constructed from the 3-input internal gates as shown by reference numeral 8 in FIG. In this case, a 6-input internal gate is constructed from the three input gate transistors 2 of one 3-input internal gate and the other 3-input internal gate, so the element part that forms unnecessary transistors and resistors will occur.

Also, as mentioned above, when using a small separately formed junction capacitance element as the speed-up capacitor 1 to increase speed, or when configuring the internal gate with CML (current mode logic),
For example, the base-emitter junction capacitance disclosed in Japanese Patent Publication No. 11810/1983 ``Transistor Logic Circuit'' is used. For this reason, there are drawbacks such as an increase in the chip size of the internal gates or the complexity of the device structure process.

[Object of the Invention] Therefore, the object of the present invention is to eliminate unnecessary elements other than those necessary to construct an n'×n input internal gate from n' n-input internal gates, both of which are expressed by integers n and n'. It is an object of the present invention to provide a capacitor-adding semiconductor device that also utilizes an element part and uses this non-element element part as a capacitor, and can increase the capacitance without increasing the element area.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, by using the junction capacitance other than the element part necessary to construct an n'×n input internal gate from n' n-input internal gates formed on the same substrate, this is added as a capacitance. In addition, it is possible to achieve a capacitor-added semiconductor device having a large capacitance without increasing the device area.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to FIGS. 4 to 6. In an embodiment described below, the capacitance-added semiconductor device of the present invention is applied to a 6-input internal gate with an NTL configuration. FIG. 4 is a diagram showing an example of the layout of input internal gates, and FIG. 5 is an equivalent 6-input internal gate circuit diagram. 6 while corresponding figures 4 and 5.
The configuration of the input internal gate will be explained. Reference numeral 9 denotes a semiconductor substrate, for example, a P-type silicon semiconductor substrate. On this semiconductor substrate 9, as an example, two three-input internal gates 10 (G ₁ , G ₂ ) are formed in each element region. Three input gate transistors 11 are formed, and as shown in FIG. 5, they are connected in parallel to each other, and their collectors and emitters are commonly connected. The base of this input gate transistor 11 is used as each input of a 3-input internal gate. A collector resistor 12 is connected to the collector of the input gate transistor 11, and an emitter resistor 13 is connected to the emitter. Voltages Vcc and _VEE are supplied to one end of the collector resistor 12 and the emitter resistor 13. On the other hand, input gate transistor 11
Between the emitter of and the terminal to which voltage Vcc is supplied,
Transistor 14 is connected. Further, the output transistor 15 for taking out an output signal from the collector of the input gate transistor 11 has its base connected to the collector of the input gate transistor 11, its collector connected to the terminal to which voltage Vcc is supplied, and its emitter Load resistance 16
It is connected to the. A voltage is applied to one end of the load resistor 16.
V _TT is supplied.

Two such three-input internal gates 10 (G ₁ ,
In order to create a 6-input internal gate with an NTL configuration using G ₂ ), basically the three input gate transistors 11 of the 3-input internal gate 10 on one side (G ₂ ) are As shown by the dotted line, it may be connected in parallel to the three input gate transistors 11 of the other (G ₁ ) three-input internal gate 10. In this case, the 3-input internal gate _G1 on the left in _FIG . Connected.

By the way, in FIG. 5, the resistors 12, 13, 16 of the 3-input internal gate _G2 are surrounded by the dotted line on the right side.
In the six-input internal gate configured as described above, the transistors 14 and 15 are portions that are not used to configure the logic, that is, non-element portions. According to the capacitance-adding semiconductor device of the present invention, the junction capacitance of these non-element elements is actively utilized. In other words, in the case of the 6-input internal gate with the NTL configuration shown in FIG. 5, these junction capacitances are added in parallel between both terminals of the emitter resistor 13 of the input gate transistor 11 to increase the speed of the 6-input internal gate by reducing the device area. This has been done without increasing. For example, a case where the junction capacitance of the transistor 14 of the gate _G2 shown on the right side in FIG. 5 is utilized will be described with reference to FIG. In FIG. 6, reference numeral 9 indicates a P-type silicon semiconductor substrate, and on this semiconductor substrate 9 are an N ⁺ type buried layer 17, an N-type epitaxial layer 18 which is a collector region, and a P-type diffusion layer 19 which is a base region. is formed. Reference numeral 20 is a field oxide film, and reference numeral 21 is an insulating film. The insulating film 21 on the P-type diffusion layer 19 in the base region is for covering the emitter of the transistor 14. Incidentally, emitters are not formed. In this state, one end of the N ⁺ type buried layer 17 and P of the base region
An electrode 22 made of Al, for example, is formed on the type diffusion layer 19. Then, the Al electrode 22 at one end of the buried layer 17 is connected to the terminal to which the voltage V _EE of the left gate G ₁ is supplied, and the Al electrode on the P-type diffusion layer 19 is connected to the input gate transistor 11 of the left gate G ₁ . It is connected to Emitsuta. Therefore, equivalently the fifth
In the figure, the emitter resistor 13 of the gate _G1 on the left side
This means that a base-collector junction capacitance, which is a junction capacitance between the P type diffusion layer 19 of the base and the N ⁺ type buried layer 17, is added between both terminals. Similarly, in the case of the transistor 15, an N ⁺ type buried layer,
The junction capacitance between the N ⁺ type buried layer and the P type base layer diffused into the N + type buried layer can be utilized.

〔effect〕

Since the junction capacitance of the non-element element portion is utilized, it is possible to reduce the element area without forming a new capacitor.

Further, since the junction capacitance of the non-element element portion can be used as a speed-up capacitance of the internal input gate, an effect of contributing to speeding up the internal input gate can be obtained.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, in the case of resistors 12, 13, and 16, the PN between the resistor region formed at the same time as the base region 19 and the N-type epitaxial layer surrounding it is
Junction capacitance can be used as well. It is preferable to use a capacitance formed between a region electrically isolated from other elements (a region formed after forming the N ⁺ type buried layer). Furthermore, other PN junctions of non-element elements can be used in the same way, taking into account limitations on the potential used and the influence on other elements.

[Field of Application] The present invention is most effective when applied to master slice LSIs, but is not limited to this. For example, when designing an LSI by regularly arranging circuit elements, the present invention can be applied to the junction capacitance of non-element elements. The present invention can be applied to

[Brief explanation of drawings]

Figure 1 shows the added speed-up capacity.
Basic circuit diagram of CML. Figure 2 shows four 3-input internal gates. Figure 3 shows two 6-input internal gates formed from four 3-input internal gates. The figure shows an example of the layout of two 3-input internal gates, FIG. 5 is a circuit diagram of an embodiment in which the capacitive addition semiconductor device of the present invention is applied to a 6-input internal gate NTL, and FIG. 6 is a diagram showing an example of the layout of two 3-input internal gates. , is a diagram showing an element structure and electrodes in the case of utilizing the base-collector junction capacitance of a transistor in a non-element element part. 1... Speed up capacitance, 2, 11... Input gate transistor, 3, 13... Emitter resistance, 17... N ⁺ type buried layer, 18... N type epitaxial layer, 19... P type in base region Diffusion layer.

Claims (1)

[Scope of Claims] 1. In a semiconductor device in which an n'×n input gate is formed by using a plurality of n' input gates formed on the same semiconductor substrate, for forming the n'×n input gate, A capacitance-added semiconductor device characterized in that a junction capacitance formed by a non-element element part other than a necessary element part is added to the n'×n input gate. 2. A patent characterized in that the junction capacitance formed by the non-element element portion is a junction capacitance between a buried layer and an impurity semiconductor region having a conductivity type opposite to that of the buried layer and forming a transistor and a resistor. A capacitance-adding semiconductor device according to claim 1.