JPH0358593A - Video recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a satisfactory reproduced picture by generating a pseudo segment vertical synchronizing pulse at suitable timing to the omission of a segment vertical synchronizing pulse and defining the generated pulse as the write start signal of a time base correcting memory. CONSTITUTION:Time width from the switching points of respective segments SEG 1-SEG 4 to the segment vertical synchronizing pulse as a reference signal for program search in each segment is stored in registers 13-16. Thereafter, when the segment vertical synchronizing pulse is not correctly detected by causes such as drop-out, etc., the pseudo segment vertical synchronizing pulse is generated after the lapse of time corresponding to the correspondent time width after the switching point of each segment, and defined as the write start signal of the time base correcting memory. In such a case, the pseudo vertical synchronizing pulse is generated at correct timing. Thus, the reproduced picture is not partially vertically deviated on a screen and the satisfactory picture can be obtained.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a video recording and reproducing device, and particularly to a video recording and reproducing device that divides one field of video signal into a plurality of segments and splits the video signal into a plurality of video tracks. The present invention relates to a helical scan type video recording and reproducing device using a segment recording method that records and reproduces data by force.

(Prior Art) Generally, in a VTR (video table recorder),
Time axis fluctuations occur in the reproduced video signal. A time axis correction circuit is used to correct this time axis variation.

FIG. 4 shows the basic configuration of a time axis correction circuit using a semiconductor memory, in which a video signal reproduced from a tape is input to an input terminal 41, and is sent to an output terminal 43 via a time axis correction memory 42. ; Output. Time axis correction memory 42
For example, it is constructed using at least two field memories each having a capacity for one field of video signals, and these field memories alternately perform write and read operations.

Writing and reading operations of video signals in the time axis correction memory 42 are performed by a write control circuit 44 and a read control circuit 45.
Each is controlled by

That is, the write control circuit 44 supplies the time axis correction memory 42 with a write clock signal and a write start signal with a period that follows the time axis fluctuation of the input reproduced video signal, and the read control circuit 45 supplies a signal with a constant period. A read clock signal and a read start signal are supplied to the time axis correction memory 42.

By the way, from the write control circuit 44 to the time axis correction memory 4
Similarly to the write clock signal, the write start signal supplied to No. 2 must follow the time axis fluctuations of the manually input reproduced video signal. As a circuit for generating such a write start signal, the configuration shown in FIG. 5 is conventionally known.

As shown in FIG. 5, this write start signal generation circuit receives a reproduction synchronization signal PB-SYNC separated from a luminance signal in a video signal reproduced by a VTR, and a horizontal synchronization pulse PB-SYNC separated from this. H is input. The reproduced horizontal synchronizing pulse PB-H is input to a field counter 51, and the output of the field counter 51 is input to a decoder 52.

On the other hand, the reproduction synchronization signal PB-SYNC is transmitted to the vertical synchronization gate 5.
3 to the vertical synchronization separator 54, where the vertical synchronization pulses are separated and extracted.

The output of the vertical synchronization separator 54 is input to the vertical synchronization comparator 55. The vertical synchronization comparator 55 is a circuit that compensates for the absence of a vertical synchronization pulse due to dropout or the like in the output of the vertical synchronization separator 54 using a pseudo vertical synchronization pulse generated from the output of the decoder 52. The field counter 51 is reset by the output of the vertical synchronization converter 55.

Then, the output of the vertical synchronization comparator 55 is delayed by a predetermined time by a delay circuit 56, and the reproduced vertical synchronization signal P
B-V is supplied as a write start signal to the time axis correction memory 42 in FIG. In this way, a write start signal that follows the time axis fluctuation of the reproduced video signal can be obtained.

If the timing of this write start signal deviates from the normal timing, the reproduced image for one track where writing is started by the write start signal will be shifted in the vertical direction of the screen, resulting in an unsightly screen. During normal playback, the timing of the write start signal rarely deviates.

However, during shuttle playback, the write start signal generation circuit shown in FIG.
Since the number of horizontal synchronizing pulses included in a scan increases or decreases depending on the shuttle speed, the count value of the field counter 51 during one scan period also increases or decreases depending on the shuttle speed. For this reason, the generation timing of the pseudo vertical synchronization pulse output from the decoder 52 is also shifted.
If a vertical synchronization pulse cannot be detected from the reproduced video signal during shuttle reproduction, the reproduced image will be shifted in the vertical direction of the screen.

In particular, in VTRs, one field of video signal is divided into multiple segments SEG1 to SEG4, as shown in Figure 2.
Recorded over multiple video tracks. In a VTR using the segment recording method shown in A, vertical 1. If the -iJ period pulse cannot be detected, the video signal for one field and two f- fields cannot be correctly written to a predetermined address in the time axis correction memory, resulting in significant disturbance of both reproduced images.

Also, even during normal playback, the switching point (
±IH (at the time of switching from segment to segment)
If a skew of more than H (horizontal scanning frequency) occurs, the timing of the pseudo vertical synchronization pulse will deviate by more than ±IH, so the timing of the reproduced vertical synchronization signal will also be deviated, and the reproduced image will be shifted in the vertical direction.

Figure 3 shows the playback signal of the segment-recorded video signal, (a) is the normal playback video signal without skew, (b)
) respectively indicate reproduced video signals when +IH skew occurs. When +IH skew occurs in this way, the pseudo segment synchronization pulse is generated before IH with respect to the normal timing. Therefore, in this case, if the segment synchronization pulse is not detected and the pseudo segment synchronization pulse is used as a write start signal for the time axis correction memory, the reproduced image will be shifted in the vertical direction on the screen.

(Problem to be solved by the invention) As mentioned above, in the conventional technology, a video signal recorded by the segment recording method is shuttle-played, and a skew occurs in a re-seated video signal at a switching point. j; If the vertical synchronization pulse cannot be detected from the reproduced video signal due to dropout etc., the timing of the write start signal of the time axis correction memory will be shifted.
There was a problem that the reproduced image was shifted in the vertical direction.

The present invention provides video playback that can correctly write the playback video signal to the time axis acquisition memory even if the vertical synchronization pulse cannot be detected during shuttle playback or when a skew occurs at the switching point of the playback video signal. The purpose is to provide equipment.

[Structure of the Invention (Means for Solving the Problems) The present invention provides a write start signal generation circuit for a time axis correction memory that corrects time axis fluctuations in a reproduction signal of a video signal recorded by a segment recording method. , measure and store the time width from the switching point of each segment of the reproduced video signal to the cue reference signal of each segment, and after a time corresponding to the time width corresponding to the segment from the switching point of each segment. The configuration is such that a pseudo cue reference signal is generated, and when the cue reference signal is detected from the reproduced video signal, the cue reference signal is output as a write speed signal, and the cue reference signal is output as a write speed signal. In cases ① and r where ``is not detected'', this pseudo cue reference signal is outputted as a write start signal.

More specifically, the time width from the switching point of each segment of the reproduced video signal to the cue reference signal of each segment is reset at the switching point of each segment of the reproduced video signal, and the first clock signal is counted. It is measured by the counter.

The time width from the switching point of each segment to the cue reference signal is stored by a plurality of registers that read the output data of the first counter at the timing of the cue reference signal of each segment.

Furthermore, the pseudo cueing reference signal is generated by a second counter into which the output data of the plurality of registers is loaded, and when the output data of this second counter reaches a predetermined value, the pseudo cuing reference signal is generated. This is done by a decoder that outputs

(Function) By measuring the time width from the switching point to the segment cue reference signal and generating the pseudo cue reference signal based on this, the switching point can be reached during normal playback. If a vertical synchronizing pulse cannot be detected when a skew of ±IH or more occurs, writing to the time axis correction memory can be started correctly using this pseudo cue reference signal, thereby making it possible to write correctly.

Furthermore, even if the vertical synchronization pulse cannot be detected during shuttle playback, by using this pseudo cue reference signal, the effect of the expansion and contraction of the time axis in one horizontal scanning period during one scan of the head can be canceled at the switching point. , the data will be correctly written to the time axis correction memory.

(Example) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a write start signal generation circuit for a time axis correction memory in a video recording and reseat apparatus according to an embodiment of the present invention. This write start signal generation circuit is, for example, the write control circuit 4 in FIG.
Located on the west side of 4.

The video recording and reproducing apparatus in this embodiment divides one field of video f= into multiple segments (in this case, 4 segments}) SEGI to SEG4, as shown in FIG. This is a segment recording type VTR that records across tracks.

In Fig. 1, terminal 1 has a playback synchronization signal PB-S.
YNC is input, a clock signal CK is input to terminal 2, a head switching pulse H-SW is input to terminal 3, and a frame pulse FP is input to terminal 4. The playback synchronization signal PR-SYNC is a synchronization signal separated from the luminance signal in the playback video signal by the VTR,
It is input to the segment vertical synchronization (SEG-V) pulse gate 5. The segment vertical synchronization pulse gate 5 is configured using, for example, a counter and a gate circuit, and detects a period in the vicinity of the segment vertical synchronization pulse using the head switching pulse H-SW and the clock signal CK, and extracts a signal within this period. The output of the segment vertical synchronization pulse separator 6 separates the segment vertical synchronization pulses.

The first counter 7 for time width measurement is activated at the edge of the head switching pulse HSW, and is activated by the clock signal C.
By counting + K, the timing of H-SW,
That is, each segment SEG1 to SEG in FIG.
Digital data indicating the time width (elapsed time) from the switching point No. 4 is generated. The output data of this counter 7 is stored in four registers 13 for storing the interval width from the switching point of each segment SEGI to SEG4 to the segment vertical synchronization pulse SEG-V, which is a reference signal for cuing up each segment. ~16 is input.

Segment counter 8 is reset at the edge of frame pulse FP and head switching pulse H SW
By counting and decoding the count value, gate signals each indicating the period in which the video signal of each segment SEGI to SEG4 is reproduced by the VTR are generated.

Gate signals indicating the video signal reproduction periods of SEG1 to SEG4 are input to one input terminal of each of AND gates 9 to 12. The segment vertical synchronizing pulse from the segment vertical synchronizing pulse separator 6 is input to the other input terminal of each of the AND gates 9 to 12. Therefore, from AND gates 9 to 12, each segment SEG1
A signal indicating the timing of the segment vertical synchronization pulse of ~SEG4 is output. That is, and gate 9-1
The output signals of 2 are segments SEGI to SEG, respectively.
It becomes high level at the timing of segment vertical synchronization pulse 4.

Registers 13-16 read and store the output data of counter 7 at the rising edges of the outputs of AND gates 9-12. Therefore, the registers 13 to 16 store and hold data of the time width from the switching point of each segment SEGI to SEG4 to the segment vertical synchronization pulse of the same segment SEGI to SEG4.

The output data of the registers 13 to 16 are input to the selector 17, and in response to a signal indicating the segment number from the segment counter 8, the output data of the register corresponding to the segment detected by the segment counter 8 is selected.

For example, when segment counter 8 detects segment SEGI, the output data of register 13 is
7 will be selected.

The output data of one register selected by the selector 17 is inverted by an inverter 18 and then provided to a second counter 19 as a load input. The second counter 19 uses as an initial value the value loaded via the inverter 18 at the edge of the head switching pulse H-SW, that is, the complement of the output data of the register selected by the selector 17, and counts the clock signal CK. . The output data of the counter 19 is input manually to the decoder 20. The decoder 20 generates a pseudo segment vertical synchronization pulse when the output data of the counter 19 reaches a predetermined value.

The pseudo segment vertical synchronization pulses output from the decoder 20 are input to the segment vertical synchronization pulse comparator 21 . When the segment vertical sync pulse separator 2 does not output a segment vertical sync pulse due to dropout or the like, this converter 21 outputs the pseudo segment vertical sync pulse output from the decoder 20 as a segment vertical sync pulse, and When the segment vertical synchronization pulse is output from the synchronization pulse separator 2, it is output as is, and the output of the decoder 20 is prohibited.

The segment vertical 1 and il period pulses output from the segment vertical synchronization separator 21 are supplied as a write start signal to the ++[i positive memory 42 between the n and +7 axes in FIG.

According to the configuration described above, each segment SEG1 to SEG
The time width from the switching point 4 to the segment vertical synchronization pulse, which is the reference signal for cueing each segment, is stored in registers 13 to 16, so that the segment vertical synchronization pulse will not be detected correctly due to dropouts etc. At this time, a pseudo segment vertical synchronization pulse is generated after a time corresponding to the corresponding time width from the switching point of each segment, and is used as a write start signal for the time axis correction memory.

In this case, the pseudo segment vertical sync pulse is created based on the special width from the switching point of each segment to the segment vertical sync pulse, so when performing shuttle playback or normal playback Hj;
Even if the above skew occurs, it will occur at the correct timing.

Therefore, when a dropout or the like occurs, the pseudo segment vertical synchronization pulse is used as the write start signal for the time axis correction memory, and the video signal for one track following this write start signal is written to the time axis correction memory. This solves the problem that the reproduced image is partially shifted in the vertical direction on the screen, and a good image can be obtained.

Note that the present invention is not limited to the above embodiments,
For example, in the format shown in Figure 2, the distance from the segment switching point to the recording position of the segment vertical synchronization pulse is segment SEGI, SEG3, S
Since EG2 and SEG3 are the same, S in Figure 1
Registers 13 and 15 corresponding to EGI and SEG3 are made common, and register 12.1 corresponding to SEG2 and SEG4 is made common.
4 can be made common to simplify the circuit. In addition, the present invention can be implemented with various modifications without departing from the scope.

[Effects of the Invention] According to the present invention, in a video recording and reproducing apparatus such as a VTR using a segment recording method, even during shuttle playback or when there is a skew of ±IH or more, it is possible to prevent missing segment vertical synchronizing pulses due to dropouts, etc. By generating a pseudo-segment vertical synchronization pulse at an appropriate timing and using this as a write start signal for the time axis correction memory, vertical image deviation (wobble) on the playback screen can be prevented.
It is possible to eliminate this problem and obtain a good re-sitting image.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a write start signal generation circuit for the unexamined axis correction memory in a video recording and reproducing apparatus according to an embodiment of the present invention, and FIG. Figures 3(a) and 3(b), which show the recording format on the tape, show a normal playback video signal with no skew of a segment-recorded video signal and a playback video signal when +IH gap occurs. Figure 4 is a block diagram showing the basic configuration of a time axis correction circuit for correcting time axis fluctuations in a video signal, and Figure 5 is a configuration of a write start signal generation circuit for a conventional time axis correction memory. FIG. 5... Segment vertical synchronization pulse gate, 6... Segment vertical synchronization pulse separator, 7... First counter, 8... Segment counter, 9-12...
AND gate, 13 to 16... register (time width storage means), 17... selector, 18... inverter,
19...Second counter, 20...De: ]-", 2
1...Segment vertical synchronization pulse comparator.

Claims (2)

[Claims] (1) A video recording and reproducing device that divides one field of video signal into multiple segments and records and reproduces them across multiple video tracks, and includes a time axis correction memory that corrects time axis fluctuations of the reproduced video signal. A video recording and reproducing apparatus according to the present invention includes means for measuring a time width from a switching point of each segment of a reproduced video signal to a cue reference signal for each segment, and a means for measuring the time width corresponding to each segment measured by the means. storage means for storing; means for generating a pseudo cue reference signal after a time corresponding to the time width stored in the storage means corresponding to the segment from the switching point of each segment; and the reproduction video signal. When the cue reference signal is detected from , the cue reference signal is output as a write start signal for the time axis correction memory, and when the cue reference signal is not detected, the pseudo cue reference signal is output. A video recording/production device characterized by comprising: means for outputting a reference signal as the write start signal. (2) The means for measuring the time width includes a first counter that starts counting clock signals from the switching point of each segment of the reproduced video signal, and the storage means includes a first counter that starts counting clock signals from a switching point of each segment of the reproduced video signal. It is composed of a plurality of registers that read the output data at the timing of the cue reference signal of each segment, and the means for generating the pseudo cue reference signal is loaded with the output data of the plurality of registers, and is configured to read the output data at the timing of the cue reference signal of each segment. and a decoder that outputs the pseudo cue reference signal when the output data of the second counter reaches a predetermined value. Video recording and playback device.