JPH0358741U - - Google Patents
Info
- Publication number
- JPH0358741U JPH0358741U JP11680389U JP11680389U JPH0358741U JP H0358741 U JPH0358741 U JP H0358741U JP 11680389 U JP11680389 U JP 11680389U JP 11680389 U JP11680389 U JP 11680389U JP H0358741 U JPH0358741 U JP H0358741U
- Authority
- JP
- Japan
- Prior art keywords
- output
- computer
- information
- generation circuit
- processing cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Safety Devices In Control Systems (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
はこの考案の一実施例においてコンピユータが正
しく動作しているときの信号タイミングの一例を
示す図、第３図はこの考案の一実施例においてコ
ンピユータが正しく動作しないときの信号タイミ
ングの一例を示す図である。
図において、１は処理周期発生回路、２はコン
ピユータ、３は機器、４は出力ウインドウ発生回
路、５はゲート回路、６は出力保護装置である。
なお、図中同一符号は同一または相当部分を示す
。
Fig. 1 is a diagram showing an embodiment of this invention, Fig. 2 is a diagram showing an example of signal timing when a computer is operating correctly in an embodiment of this invention, and Fig. 3 is an example of an embodiment of this invention. FIG. 6 is a diagram showing an example of signal timing when the computer does not operate correctly in the embodiment. In the figure, 1 is a processing cycle generation circuit, 2 is a computer, 3 is a device, 4 is an output window generation circuit, 5 is a gate circuit, and 6 is an output protection device.
Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
回路から出力されるパルスに同期して一連の処理
を行うコンピユータと、このコンピユータから出
力される情報によつて制御される機器との間にあ
つて、コンピユータが誤動作したとき上記機器に
対して誤つた情報が出力されないようにするため
の出力保護装置において、前記処理周期発生回路
から出力されるパルスを基準としてコンピユータ
から機器に対して情報が出力されるべき時刻及び
時間を管理している出力ウインドウ発生回路と、
この出力ウインドウ発生回路からの指示で、コン
ピユータから機器へ情報が出力されるべきときだ
け情報を出力できるようにするゲート回路とで構
成したことを特徴とする出力保護装置。 Between a computer that performs a series of processes in synchronization with the pulses output from a processing cycle generation circuit that generates pulses at a certain period, and equipment that is controlled by the information output from this computer, In an output protection device for preventing erroneous information from being output to the above device when the computer malfunctions, information is output from the computer to the device based on the pulse output from the processing cycle generation circuit. an output window generation circuit that manages the desired time and time;
An output protection device comprising a gate circuit that allows information to be output from a computer to a device only when information should be output based on instructions from the output window generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11680389U JPH0358741U (en) | 1989-10-04 | 1989-10-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11680389U JPH0358741U (en) | 1989-10-04 | 1989-10-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0358741U true JPH0358741U (en) | 1991-06-07 |
Family
ID=31665066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11680389U Pending JPH0358741U (en) | 1989-10-04 | 1989-10-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0358741U (en) |
-
1989
- 1989-10-04 JP JP11680389U patent/JPH0358741U/ja active Pending
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