JPH0359507B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock reproduction method when recording and reproducing digital codes.

For data reproduction, it is necessary to reproduce a clock signal synchronized with the digital input signal.
As a method of obtaining such a clock signal, in the case of an asynchronous clock using an oscillator, the system shown in the block diagram of FIG. 1 can be considered. 1 is an oscillation circuit that oscillates at a frequency of N/T; 2 is a frequency divider circuit that divides the output of 1 by N; 3 is a clock signal with a frequency of 1/T that is the output of frequency divider circuit 2 and is used for data reproduction; 4 is an input terminal for the binarized data input signal, 5 is a delay circuit, and 6 is an exclusive OR circuit that receives the outputs of input terminal 4 and delay circuit 5, and its output is the reset signal of frequency divider circuit 2. served. Next, the operation of the configuration shown in FIG. 1 will be explained with reference to FIG. 2. Here, T is the correct period of one bit of the input signal, the most frequently occurring element length, and the minimum pulse width. When A is the input signal of input terminal 4,
B is the output of the exclusive OR circuit 6, and C is the clock signal 3. However, as shown in D, at time _t1 , a signal that is shifted backward from the normal position is input to input terminal 4.
When the input signal is E is the output of the exclusive OR circuit 6, and F is the clock signal 3.

That is, the width of each element of the input signal becomes longer or shorter due to noise and various distortions during recording and reproduction. D is an example in which the element becomes long from t ₁ to t ₂ , which may affect F and cause data reproduction to be erroneous.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock regeneration method that regenerates a stable clock signal regardless of the above-mentioned distortion of the input signal.

Therefore, the present invention is to check whether the input signal has been distorted based on the modulation rules, and to use it as a reset signal for the frequency divider circuit only when the input signal is normal.

Embodiments illustrating the present invention will be described in detail below. FIG. 3 is a block diagram showing the configuration of one embodiment of the present invention, in which 12 is an input terminal for a data input signal, and 13 is a block diagram for detecting the T, T, and T pulse widths input to the data input terminal 12. do
3N1 stage shift register circuit, 14 and 16 have N1 inputs, and logic circuits that output "1" when all inputs are "0"; 15 has N1 inputs, and all inputs are "1" “1” when
17 is a logic circuit 14, 1 that outputs
The outputs of 5 and 16 are input, and all inputs are “1”
The AND circuit that outputs “1” when , 7 is
An oscillation circuit that oscillates at a frequency of N ₀ /T, 8 a frequency divider circuit with a frequency division ratio N ₀ /N ₁ that inputs the output of the oscillation circuit 7, and 9 a frequency divider that inputs the output of the frequency divider circuit 8. A frequency dividing circuit with a ratio N ₁ , 10 is a frequency N ₁ / which drives the shift register circuit 13 with the output of the frequency dividing circuit 8.
The output of the AND circuit 17 is a reset signal for each of the frequency dividers 8 and 9. Served.

Next, the operation of the configuration shown in FIG. 3 will be explained with reference to FIG. 4. When G is the input signal of the input terminal 12, the output of the AND circuit 17 becomes H, and I
becomes the clock signal 11. Although G is shifted backward from its normal position at _t1 , there is no output from the AND circuit 17, and the frequency divider circuits 8 and 9 are not reset, and the clock signal 1 remains in the same phase as before.
1 is retained. The logic circuit 16 detects that G is "0" between t ₂ and t ₃ , the logic circuit 15 detects that G is "1" between t ₃ and t ₄ , and the logic circuit 15 detects that G is "1" between t 3 and t ₄ .
Since the logic circuit 14 detects that G is "0" during t ₅ , the AND circuit 17 outputs an output at t ₅ , and the frequency divider circuits 8 and 9 are reset, but the clock signal 11 is The clock signal 11 is held almost in phase with the previous phase, and the frequency divider circuits 8 and 9 continue to hold the clock signal 11 until the next output from the AND circuit 17 arrives.
is continued by the frequency divider circuit.

As described above, according to the present invention, it is easy to obtain a clock signal that is always synchronized with the input digital signal, which was a major problem in the past, and the pulse widths of T, T, and T, which occur most frequently, are tested. The structure requires only the smallest stage shift register, and the quality of information demodulated from the clock signal can be dramatically improved.

In this embodiment, the logic circuits 14 and 16 are changed to a logic circuit 15 that outputs "1" when all inputs are "1", and a logic circuit 15 that outputs "1" when all inputs are "0". Even if you change the input logic conditions,
A similar effect can be obtained.

[Brief explanation of drawings]

Figure 1 is a clock regeneration circuit diagram according to the prior art.
FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of the clock recovery circuit according to the present invention.
FIG. 4 is an explanatory diagram of the operation of FIG. 3. 13...Shift register, 14, 15, 16...Logic circuit.

Claims (1)

[Scope of Claims] 1. A clock reproduction method that digitally modulates a digital signal, records it on a recording medium, and reproduces a clock used in a circuit that digitally demodulates the reproduced digital signal obtained from the recording medium during reproduction. , an oscillating means, a frequency dividing means for frequency dividing the output signal of the oscillating means, a pulse width testing means to which a reproduced digital signal is supplied and for inspecting the pulse width of the reproduced digital signal, and an output signal of the pulse width testing means. and control means for setting the frequency dividing means to an initial state, and regenerating a clock synchronized with a reproduced digital signal. 2. The clock regeneration method according to claim 1, wherein the pulse width testing means comprises a shift register to which a reproduced digital signal is supplied, and a logic circuit to which an output signal of the shift register is supplied.