JPH0359627B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television switcher control system.

Conventionally, when controlling video switchers using a computer, it has been difficult to switch a plurality of switchers at the same timing. This is because the computer and the input/output interface use bus lines to transmit signals in a time-division manner, so even when simultaneous control is required, the control is performed sequentially with a slight time difference. For this reason, switching may not occur at the timing of the same vertical period of television (for example, the same vertical blanking period), which has been a problem.

Also has been done to solve this kind of problem,
A system in which a latch circuit that latches at computer timing is followed by a latch circuit that latches at the same vertical timing requires two stages of latch circuits, which poses problems in terms of economy and reliability.

SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a video switcher control system which eliminates the drawbacks of the prior art and allows a plurality of switchers to be switched at the same timing without using two stages of latches.

According to the present invention, in addition to the first latch circuit that latches data from the computer at the computer timing, there is also a gate circuit that is turned on and off by the trigger (vertical trigger pulse) of the television vertical timing, and the first latch circuit latches the data from the computer at the computer timing. By controlling the output of the circuit with a gate circuit, it is possible to obtain a video switcher control system that solves the above drawbacks and makes it possible to switch a plurality of video switchers at the same timing.

Next, the present invention will be described in detail with reference to the drawings of an embodiment of the present invention.

The drawing is a block diagram illustrating an embodiment of the present invention.

Although this embodiment describes the most basic simultaneous control operation of two related video switchers, any number of video switchers greater than or equal to two can be controlled using a similar method. In the drawing, 11 is a computer timing clock pulse input terminal, 12 is a first latch circuit, and data input via the data bus line DB is input to the latch circuit 12 by the clock pulse input terminal 11 from the computer. It is latched at the timing of 31 is an input terminal for the switcher control output signal output from the computer;
The input signal to this is latched by the second latch circuit 32 at the timing of the computer clock pulse sent from the computer via the terminal 61. 33 is a third latch circuit which relatches the output of the second latch circuit in response to a vertical trigger pulse input from terminal 51. A gate circuit 13 gates the output of the first latch circuit 12 using the output of the third latch circuit 33. Terminal 41 is an input terminal for a reset signal based on computer timing.

The clock pulse input terminal 21, the first latch circuit 22, and the gate circuit 23 constitute another video switch control circuit.
It corresponds to the first latch circuit 12 and the gate circuit 13.

Now, there is a switcher controlled by the input terminal 11, the first latch circuit 12, and the gate circuit 13 (hereinafter referred to as the front row switcher), and a switcher controlled by the input terminal 21, the first latch circuit 22, and the gate circuit 23. (hereinafter referred to as the rear row switcher) will be described below. When controlling the related switches, the computer transmits the switch information of the front row and the rear row in a time-sharing manner via the data bus line DB, and these are sequentially transmitted to the first latch circuits 12 and 22.
is held.

In this way, related switch information is transmitted to the latch circuit in a time-division manner, so the timing at which it is held will never be the same.

After transmitting the switch information, the second latch circuit 32 is turned on at the computer timing by receiving a switch control output signal from the computer at the terminal 31. The ON signal of the second latch circuit is applied to the third latch circuit 3 by a vertical trigger pulse.
3 is turned on, gate circuits 13 and 23 are opened at exactly the same timing, and related video switchers are controlled at the same timing. The control signal of the video switcher is reset to a pulsed control signal by a reset signal output from the computer after a certain period of time has elapsed.

As explained above, the present invention uses a gate circuit and a two-stage latch circuit that controls the gate, and controls the timing pulse applied to the subsequent latch circuit with the vertical trigger pulse, thereby controlling the related video switch with the vertical trigger pulse. This makes it possible to switch at the same timing as the switch, and its industrial value is extremely large.

[Brief explanation of drawings]

The drawing is a block diagram showing one embodiment of the present invention. In the figure, 11, 21, 61... CPU timing clock pulse input terminal, 12, 22...
first latch circuit, 13, 23... gate circuit,
31...CPU timing control output signal input terminal,
41... Reset signal input terminal, 51... Vertical trigger pulse input terminal, 32... Second latch circuit, 33... Third latch circuit.

Claims (1)

[Claims] 1 A video switcher control system in which a plurality of video switchers are controlled by a computer, the plurality of video switchers being provided corresponding to each of the plurality of video switchers and latching switch designation data from the computer at the timing of execution of a command by the computer. a first latch circuit, a second latch circuit that latches the switcher control output signal from the computer at the computer's instruction execution timing, and a third latch circuit that latches the output of the second latch circuit at the timing of television vertical synchronization. a latch circuit, and a plurality of gate circuits provided corresponding to the plurality of video switchers, respectively controlling the outputs of the plurality of first latch circuits with the outputs of the third latch circuits, A video switcher control system characterized in that each of the plurality of video switchers is switched by the output of the plurality of gate circuits.