JPH0359736A - Image information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is useful for displaying and printing images of drawings and documents stored in storage media such as optical disks, and for using communication means. The present invention relates to an image information processing apparatus that electronically performs comprehensive processing such as using the image information to transmit the information to others, and furthermore, to edit it.

(Prior art) In recent years, document images such as general documents and drawings are stored in large-capacity storage media such as optical disks, and these can be electronically managed, displayed, printed, transmitted, and can be used to add text or text to them. A system that handles document images in an integrated manner, such as by adding graphics, is attracting attention.

In such a system, the image information stored in the large-capacity storage medium is loaded into a bitmap memory composed of, for example, RAM (random access memory), and edited and other various processes are performed on this bitmap memory. After being applied, it can be used for display, printing, transmission, etc.

Since such accesses to the bitmap memory occur frequently, the access speed and processing efficiency are important factors that influence the performance of the entire image information processing apparatus. Therefore, various measures have been taken to speed up the access and improve processing efficiency, but there has been no system that efficiently processes these processes in an integrated manner to meet user demands.

Furthermore, when dealing with only a 2-bank configuration, it is possible to access 1 to N/2 bits of data from any bit address, and it is easy to control addresses and data processing in bitmap memory processing. Since the configuration requires a data width of N bits, many data lines are required, and even though the memory configuration is N bits, the data width is N/2.
The drawback was that it could only access bits.

In addition, when the memory is configured as one bank, N bits can be accessed, but when accessing 1 to N bits from an arbitrary bit address, data processing control based on the bit address and access data width is complicated. If you access across word boundaries, not only
Even when the access data width is short, it is necessary to change the address and perform memory access twice, which has the disadvantage of slowing down the access speed.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image information processing device capable of faster and more efficient vitomap processing with a simple configuration. With the goal.

[Structure of the Invention] (Means for Solving the Problems) An image information processing device of the present invention stores image information input with an input device in a storage medium, and transfers the image information to the storage medium as necessary. In an image information processing device that reads and outputs data from a computer, the first access unit has an access data width of N/2 bits and the second access unit has an access data width of N/2 bits. First,
storage means for storing the image information whose access data width becomes N bits by simultaneously accessing the second access unit; address generation means for generating an address to be supplied to the storage means; an addition means for incrementing a given address; a switching means for switching whether the access to the storage means is a data access from a 1-bit width to an N/2-bit width or an N-bit width data access; When the means is switched from 1-bit width to N/2-bit width data access, if the address generated by the address generation means specifies the first access unit α, that address is and a second access unit, and if the address generated by the address generation means specifies the second access unit, the address is incremented by the addition means to the second access unit. supplies an address to the first access unit, and supplies an address generated by the address generation unit to the first and second access units when the switching unit switches to N-bit width data access; The invention is characterized in that it is equipped with a control means.

(Operation) The present invention uses a storage means that is composed of, for example, a first access unit and a second access unit and is compatible with either a one-bank configuration or a two-bank configuration, and stores data in a large access area, such as a rectangular area. When accessing, that is, when N bits are accessed from an arbitrary bit address, assuming the data width in a 1-bank configuration is N, the storage means is treated as having a 1-bank configuration.On the other hand, when accessing by a complex address such as affine transformation, for example, In other words, when accessing data from 1 to N/2 bits from any bit address, it is possible to switch so that it is handled as a 2-bank configuration, which makes it easier to generate addresses in the case of a 1-bank configuration, and it is also faster and faster. Processing is possible with relatively simple control, and in the case of a 2-bank configuration, data processing can be performed easily.
It is capable of high-speed processing.

(Example) Hereinafter, one example of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of an image information processing apparatus according to the present invention.

1 in the figure is a central processing unit (hereinafter referred to as rCP UJ), which controls and controls each module of this image information processing device.
It performs management, calculation processing, etc.

2 is a direct memory access control unit (hereinafter referred to as “DMA
J), and includes an external device and a program memory device 3.
This is to execute data transfer at high speed between the program memory device 3 or within the program memory device 3.

The above-mentioned external devices include a hard disk device 16 and a hard disk controller (IDC) 4 that controls it, a floppy disk device 17 and a floppy disk controller (FDC) 5 that controls it, and a user who can give instructions to this device and write text. A keyboard 18 used for inputting information, a mouse 19 which is a pointing device for pointing a specific part of the screen displayed on the display, and peripheral input/output control that controls them and receives data. Part (PI○) 6 is prepared. These are connected to a peripheral data input/output bus (hereinafter referred to as rPIO bus j) 26, and are connected to the above-mentioned CPUI and DMA2.
Under the control of the program memory device 3, high-speed data transfer is possible. In addition, the CPU bus control logic controller (CBL) 7 enables the above-mentioned data transfer to other devices/control units via the system bus 25. For example, the second
The configuration is as shown in the figure. That is, under the control of the bus arbiter (ARBT) 30, the gates 32a to
32f is opened and closed to interconnect the CPUI, DMA 2, program memory device 3, system bus 25, or PIO bus 26.

The communication processing control unit 8 performs processing such as protocol control for transmitting and receiving data to and from other external devices via the communication line 20, and data bucketing/unpacking. The data is the CPUI, D
It is exchanged with the program memory device 3 and the like under the control of MA2.

The optical disk control section 9 controls the optical disk device 21.

The display control unit 10 includes a memory (hereinafter referred to as rDPM) consisting of a dual port memory device that stores image data.
In order to display a part of 11 (referred to as J) on the display section 22, the DPMI 1 has a function of reading out display data from the display section of the DPMI 1 and sending it to the display section 22 together with a synchronization signal. Furthermore, the DPMI 1 has not only a function as a memory for simply storing image data, but also various drawing functions (details will be described later). Image processing section 12
performs image conversion processing such as linear density conversion and enlargement/reduction conversion of image data, and encoding/decoding processing such as compression/expansion processing of image data. Further, the scanner control unit 13 controls an image scanner device (hereinafter referred to as "scanner") 23 that reads and inputs image data from paper, etc., and transfers the data to the DPMI 1. The printer control section reads data from the DPMll, transfers the image data to an image printer device (hereinafter referred to as "printer") 24, and performs control to print it out on paper.

The scanner control unit 13 and printer control unit 14 are connected to an image data input/output bus (hereinafter referred to as RL10 bus) 27, and are capable of high-speed data transfer with the DPMll. In addition, the image bus control logic control unit (rlBLj hereinafter) 15 handles all data transfer related to image data, including data exchange with other devices and control units via the system bus 25. The bus arbitration is controlled so that these operations can be executed in parallel, and has a configuration as shown in FIG. 3, for example. That is, under the control of the bus arbiter (ARBT) 3B, the gates 36a to 36g are opened and closed to interconnect the DPMI 1, the image processing unit 12, the system bus 25, or the 110 bus 26.

Next, details of DPMI 1 will be explained with reference to FIG. 4. The memory 50 is composed of two parts, a display memory DM and a page memory PM, and stores image data and code data. The display memory DM is constituted by a dual port memory, and is adapted to read video data from the serial port SD and display it on the display section 22. In addition, the page memory PM is
It is composed of general-purpose DRAM (dynamic random access memory) and can be treated as a one-dimensional memory. The memory 50 has a two-bank configuration, and is divided into an even bank (first access unit) and an odd bank (second access unit).

The address generator 51 generates an address when accessing the memory 50. This address generation section 5
1 has four systems of independent address generators 70, 71, 72, 73, as shown in FIG. The configuration is such that it is possible to select from among the system addresses that come and output them.

The address generators 70, 71 and 72, 73 are two-dimensional address generators, respectively, and are capable of generating bit addresses using affine transformation or the like. The selector 74 selects one address from the two-dimensional addresses and system addresses generated by the address generators 70.71 and 72.73. The two-dimensional address selected here is processed by the two-dimensional to one-dimensional converter 75.
, window signal generator 76, and access width control section 7
7. The two-dimensional to one-dimensional converter 75 performs a process of converting a two-dimensional address into a one-dimensional address as necessary. In other words, X address is XADSY
If the address is YAD and the scanning width in the X direction is XW, then r
A one-dimensional address can be obtained by XW*YAD×XADJ.

In addition, in the window signal generator 76, by comparing with a preset window address, the window signal, that is, the WND representing the inside of the window is generated.
A signal, an LWND signal indicating that the left edge of the window is being accessed, and an RWND signal indicating that the right edge of the window is being accessed are generated. In this embodiment, two systems of window signals are provided corresponding to each channel. The access width control unit 77 controls the data width to be accessed for the generated address. Further, the selector 78 selects an address from the two-dimensional to one-dimensional converter 75 or a one-dimensional system address. The adder 79 is an arithmetic unit that performs address calculation to provide the next address to one bank when the memory 50 is divided into two banks. The selector 80 selects either the current address or the next address in the memory 50 calculated by the adder 79.

The latches 56 and 61 shown in FIG. 4 are a latch 56 that stores addresses in odd banks of the memory 50 and a latch 61 that stores addresses in even banks among the addresses from the address generator 51, respectively.

The data processing section 52 is configured as shown in FIG. 6, and performs data processing such as enlargement, reduction, ternary operation, and clipping. Further, at this time, data processing of 1 to 32 bits or 64 bits from an arbitrary bit address is possible. The latch 88 temporarily stores data read from the memory 50, and
Reference numeral 6 stores patterns to be drawn in the memory 50. The contents of this pattern RAM 86 can be rewritten. The data processing unit 85 includes a register for temporarily storing data, a barrel shifter for shifting data according to an offset address, a scaling unit for scaling processing, and a data weight (LSB-MS).
It is comprised of an inversion processing section (none of which is shown) that inverts the image (B). Further, the ALU 87 performs a ternary operation, that is, pattern data from the pattern RAM 86, source data from the data processing unit 85, and memory 5.
A ternary operation is performed with the destination data from the latch 88 that stores data starting from 0. During this ternary operation, the mask processing unit 90 uses the ALU 87
A mask is created to distinguish between the parts where calculations are performed and the parts where no calculations are performed. This mask creation is determined by the offset address, window signal, and access width input from the address generator 51. Furthermore, the data processing section 52 includes a boundary detection section 89 for supporting filling.

This boundary detection section 89 detects whether there is a "1" or "0" in the data input from the memory 50.

The sequencer 53 shown in FIG. 4 has a function of generating control signals for the address generation section 51, data processing section 52, and memory control section 54 during memory access.

The memory control unit 50 controls the memory 50.
It generates an AS signal, a CAS signal, an OE multiplied signal WE signal, etc. As described above, the display control section 10 controls the display section 22, and the display address output from this section is supplied to the selectors 57 and 58. Then, in the selectors 57 and 58, one of the address from the display control section 10 and the address supplied from the address generation section 51 is selected and supplied to the memory 50.

Further, the address from the display control section 10 is sent to the cursor control section 55, and the cursor is displayed at an appropriate position on the display section 22 by comparing it with preset cursor position information.

Furthermore, the H3YNC signal and VSYNC signal output from the display control section 10 are used as synchronization signals in the display section 22. The shift register 59 converts display data read from the memory 50 into serial data. The synthesizing section 60 synthesizes the display data supplied from the memory 50 via the shift register 59 and the cursor data supplied from the cursor control section 55, and displays the data on the display section 22.

Next, regarding the operation of DPMII in the above configuration,
A detailed explanation including the operation of peripheral hardware will be provided.

When accessing the memory 50 in DPMI I, an access request (A
By issuing a CC request and performing arbitration by the ARBT 33, only one access request is selected when multiple access requests conflict.

When the ARBT 33 determines whether access is permitted, the sequencer code is supplied to the sequencer 53, and the sequencer 53 starts operating and controls the memory 50 and the like.

In this embodiment, there are four types of accesses to DPMll. In other words, IO access from the scanner 23 and printer 24, and C
These are CPU access which is access from PU1, rask processing access when performing image processing using image processing unit 12, and internal access which is access within DPMI I.

Each of the above accesses will be explained below. Scanner 23
10 accesses regarding image input from CP
The UI first sets parameters for each relevant module. At this time, the address supplied to the memory 50 is supplied to the address generator 70 of the address generator 51,
Use one of 71, 72, 73. Scanner 23
When the scanner starts operating, the read data is sent to the scanner control section 13, and the scanner control section 13 receives this data 'E.
-110 bus 27 data bus width, ARBT3B
A request to write data to DPMI 1 is issued to the DPMI 1. If there is no other access request, the ARBT 3B controls the gate 36a and transfers information from the scanner control units 13 to 11.
The read data of the scanner 23 sent via the 0 bus 27 is supplied to the DPMI 1, and the sequencer code is sent to the sequencer 53 at the same time. As a result, the sequencer 53 starts writing data to the memory 50 in the DPMI I. That is, the address generator 5
Select the corresponding address from 1, switch to odd address and even address sequentially, and latch 56 and 61 respectively.
Latch to. Next, the selectors 57 and 58 are connected to the latch 56.
．． The address from 61 is selected and supplied to memory 50. On the other hand, the data is subjected to data processing in the data processing section 52 and written into the memory 50. At this time, a control signal for the memory 50 is generated by the memory control section 54. When the data writing is completed, the sequencer 53
An arbiter control signal indicating termination is output to the RB 733, and the ARB 733 further outputs an termination signal to the scanner control unit 13, thereby completing one data transfer. By repeating this operation, the image data for one sheet read by the scanner 23 is stored in the memory 50, and the input operation is completed.

Regarding image output to the printer 24 in 10 accesses, the CPUI first sets parameters for each relevant module.

At this time, one of the address generators 70, 71, 72, and 73 of the address generator 51 is used to supply the address to the memory 50. When the printer 24 starts operating, the printer control unit 14 sends the A
A request is issued to the RBT 33 to read image data from the DPMII. If no other access request is received, the ARBT 33 controls the gate 36a and simultaneously sends a sequencer code to the sequencer 53. As a result, the sequencer 53 starts reading image data from the memory 50 in the DPMI I. That is, the corresponding address is selected from the address generator 51, and the odd address,
The latches 56 .
Latch to 61. Selectors 57.58 then select the address from latch 56.61 and supply it to memory 50. - On the other hand, a control signal for the memory 50 is generated by the memory control unit 54, and image data is read from the memory 50. The read image data is subjected to data processing, that is, shift processing, mask processing, etc., in the data processing section 52, and is output to the IIO bus 27 through the game 136a. The sequencer 53 outputs an arbiter control signal indicating termination to the ARBT 33, and further outputs an arbiter control signal to the ARBT 33.
outputs an end signal to the printer control unit 14 to notify that reading of the image data has ended. As a result, the printer control unit 14 receives the image data and outputs it to the printer 24, thereby completing one data transfer. This operation is repeated to read out image data for one page from the memory 50 and output it to the printer 24, thereby completing the output operation to the printer 24.

Next, access to the memory 50 by the CPU will be explained. The CPU 1 issues a read or write access request to the memory 50 in the DPMll to the ARBT 33 via the system bus 25. A
In response to this request, if there is no access request to other DPMlls and the arbiter allows it, the RB733 controls the game controller 36a and further outputs a sequencer code for CPυ access to the sequencer 53. do.

The sequencer 53 thereby starts accessing the memory 50. The system address from the CPUI is input to the address generator 51 of the DPMI 1 via the system bus 25.

This system address is output via the selector 78.80 in the address generator 51, and is output to the latch 56.61.
latched to. The output of this latch 56.61 is supplied to the memory 50 via a selector 57.58. In the case of reading, data is read from the memory 5° by a control signal from the memory control unit 54, and is sent to the CP via the data processing unit 52, the game 36a, and the system bus 25.
Sent to UI. Regarding writing, data from the CPU is written to the memory 50 via the system bus 25, the game controller 36a, and the data processing section 52. Although the data width of the memory 5o is 64 bits, the data processing unit 52 selects data based on the lower α bit of the address and accesses the corresponding data. Note that during writing, write control is performed by outputting a write-enough (WE) signal from the memory control unit 54.

Next, regarding rask processing access, a case where image reduction processing is performed using the image processing section 12 will be described here. First, parameters are set for each module to be used using the CPUI. In this embodiment, the image data read from the memory 50 is
34 (see FIG. 3) and write the reduced image data to another address in the memory 50 again. Use two of these.

When the process starts, first, the LDC 34 connects the ARBT 3
A request to read image data from the memory 50 is issued to the device B. When the ARBT 33 accepts this, it outputs a sequencer code for external read access to the sequencer 53, whereby the image data is read from the memory 50 and sent to the LDC via the data processing unit 52 and the game controller 36a.
34, and the read operation is completed.

At this time, the source side of the two address generators is used as the address. This readout operation is performed over several lines of the image, and is stored in a line buffer (not shown) provided for the LDC 34 to perform interpolation processing. When an appropriate amount of image data is stored in the line buffer of the LDC 34, the LDC 34 sends a write request to A.
Output to RBT33. The ARBT33 outputs the sequencer code for external write access to the sequencer 53,
A write operation is started. That is, the destination address generator of the address generator 51 is selected, and the reduced image data output from the LDC 34 is used as a game).
36a, the data is written to the memory 50 via the data processing section 52.

The operation ends by performing the above processing for one image.

Next, internal access within the DPM 11 will be explained.

There are multiple types of internal access. That is, there are copy accesses for copying data to another address, swap accesses for exchanging data, and drawing accesses for drawing patterns and the like. All these accesses are controlled by sequencer 53 within DPMII. Further, the address at this time is obtained from the address generator 51, and in the case of copy access and swap access, two of the address generators 70, 71, 72.degree. 73 are used. When the access mode is set in the internal sequencer inside the sequencer 53, an internal access request is issued to the ARBT 33. This allows ARB
When the T33 accepts the internal access, it supplies the sequencer code to the sequencer 53, the sequencer 53 accesses the memory 50 using the address of the address generator 51, and the data processing unit 52 processes the data. Let's do it. Here, the address generation unit 51 is capable of generating not only addresses of a simple rectangular area, but also affine transformation addresses such as rotation, trapezoidal addresses, etc., and copy access using these can be performed. It has become.

Next, memory access according to the present invention will be explained in more detail.

First, a case will be described in which the memory 50 is accessed in a two-bank configuration. FIG. 7 shows the configuration of the memory 50 and the access portion (shaded portion) at that time. The memory 50 has a data width of 32 in both even and odd banks.
It has a bit configuration, and when considering a two-dimensional memory configuration, the convergence in the X direction is defined as XW.

For access ■, the bit address is ADO, and the data access width ACW is I F +b (the subscript "16" indicates hexadecimal notation). Here, the access width ACW is a parameter set in the address generation unit 51, and the actual access width ACW is 2016, which is IF+6 plus "1", that is, 32 bits. This access width IF+6 is set in the ACW register 91 of the address generator 51 (see FIG. 11). For access ■, the bit address is ADI and the access width is 1816. Here, access ■ is the last access of the line,
The access width 18.6 at this time is the final access width ACW
It is set as E in the ACWE register 92 of the address generator 51 (see FIG. 11).

Next, details of this two-time memory access operation per line will be explained with reference to the timing chart of FIG. When channel CH○ of address generation section 51 is selected by sequencer 53, ADO is output to address MAD. This ADO is a bit address, the lower 6 bits of which are input to the data processing unit 52 as an offset address, the upper address A is input to the latch 56.61, and the address latch clock OL of the odd address
T is temporarily stored in the latch 56.

Next, the address select signal ADSC is input to the address generator 51 to generate an even address.

The even number address generation circuit at this time is shown in FIG. This is a detailed diagram of adder 79 shown in FIG. That is, the address (
Upper 24 bits of AD329~O) (AD529~6)
is input to one input terminal of the seven adders, and ADS5 inputs r
In the case of lJ, the adder 790 adds “
1" is added, and if it is "0", it is output as is. That is, when ADS5 is "1", it means that an odd bank is being accessed, and therefore, as an even address at this time, an address obtained by adding "1" to the upper address is used. In this embodiment, first, regarding access ■, ADO indicates an even bank,
Since ADS5 is “0”, the same AD as the odd address
O is output from the address generator 51, and the upper address A is temporarily stored in the latch 61 by the latch clock ELT. This causes the same address A to be set to selector 57.58.
lJt is supplied to the memory 50 via. On the other hand, since the line final access signal EOLN is at a low level, the access width is selected from the value set in the ACW register 91 in FIG. 11, and IF16 is input to the data processing unit 52 as the access width. The mask processing section 9 of the data processing section 52 uses this access width IF+6 and the offset address.
0, a mask is generated, the ALU 87 performs data processing on only the accessed portion, and the data is written into the memory 50. Similarly, in access ■, first,
Odd address is upper address A of bit address ADI
is temporarily stored in the latch 56 by the latch clock OLT, and then switched to an even address by the address select signal ADSC. At this time, ADI indicates an odd bank, so the offset address (lower 6 bits) remains unchanged. , F with "1" added to the upper address
The address of A+IJ is output and temporarily stored in the latch 61 by the ELT signal.

Therefore, address A is given to the odd numbered bank, address rA+IJ is given to the even numbered bank, and the memory 5
0 will be accessed. As for the access width at this time, since the EOLN signal is output from the address generation section 51, the access width set in the ACWE register 92 in FIG. 11 is selected and input to the data processing 852.

In the data processing unit 52, a mask is created in the mask processing unit 90, as in the case of access (2), and the ALU 87 performs data processing on only the accessed portion, and the data is written into the memory 50.

In this way, by arranging the memory 50 to have a two-bank configuration so that addresses can be given independently to the even and odd banks, data access of 1 to 32 bits can be easily performed from any bit address. ,
Since the line final access width can be controlled, the access width of one line can be set arbitrarily.

Next, 64-bit access when the memory is treated as one bank will be explained. FIG. 12 shows the memory 50
FIG. 3 is a diagram showing the state of a memory when accessing it as a bank. In this embodiment, a case will be explained in which three memory accesses are required.

First, the bit address in the first access ■ is AD
O, and in 64-bit access, addresses are generated in 64-bit units in the address generator 51, so the addresses for access ■ and access ■ are r
ADl-ADO+64'', rAD2-ADO+128J
The address will be . First, regarding access ■,
The sequencer 53 selects CHI as the address channel, and thereby the address generator 51 outputs the bit address ADO. The offset address of the lower 6 bits of the address is input to the data processing unit 52, and the upper address is input to the latch 56.6 using the latch clock of the ELTSOLT signal at the timing shown in FIG.
1 are temporarily stored. In this 1-bank mode, the access width used in the 2-bank mode is not used, and since CHI is set in advance to be in the 1-bank mode in the data processing unit 52, the access width is normally 3F16, i.e. , treated as 64-bit access. When the line start signal 5OLN indicating the first access of one line is supplied from the address generation section 51 to the data processing section 52, the line start signal 5OLN, which is set in advance in the ASM register 95 of the mask processing section 90 of the data processing section 52, is supplied to the data processing section 52. A mask is created using the offset address ASM, and data is written from ADO to the next 64-bit word boundary, as shown in FIG.

Next, regarding the access (2), the next address ADI is generated from the address generator 51, and written to the memory 50 in the same manner as above. However, the access (2) is neither the first access nor the final access of one line, and therefore the 5OLNSEOLN signal is disabled, so the data processing unit 52 accesses all bits with an access width of 64 bits. Finally, regarding the access (2), the memory is accessed with the bit address AD2, but since the access (2) is the final access of the line, the EOLN signal is enabled. Therefore, in the data processing section 52, the mask processing section 90
A mask is created using the offset address ESM preset in the ESM register 96 of the memory word boundary address rA+2J, as shown in FIG. FIG. 14 shows a block diagram of a mask generation section using line signals in the 1-bank mode in the section 90.

As mentioned above, the access data width when configuring one bank is N
Then, when accessing N bits from an arbitrary bit address, by treating the memory as one bank configuration, address generation becomes easy and processing can be performed at high speed and with relatively simple control. Further, for data access of 1 to N/2 bits from an arbitrary bit address, by adopting a two-bank configuration, data processing can be easily performed and high-speed processing can be performed.

By incorporating an address calculation unit for even banks, which is necessary in this two-bank configuration, into the address generator, and making it possible to select between odd and odd addresses using a selector,
In one memory system, it becomes possible to handle both bitmap processing with a one-bank configuration and bitmap processing with a two-bank configuration. Furthermore, by controlling the access width and generating a mask, it is possible to access data from any bit address.In addition, in 1-bank mode, access to large rectangular areas can be speeded up, and in 2-bank mode, complex memory access can be This can be done with simple control.

In addition, data processing in bitmap memory can flexibly respond to the access data width, which not only enables high-speed processing depending on the processing, but also facilitates address generation and data processing. By implementing an LSI with a configuration in which the calculation section is built into the address generator, a more compact and high-performance bitmap memory system can be constructed, and in turn, a more compact and high-performance image information processing device can be provided.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide an image information processing apparatus that is capable of faster and more efficient bitmap processing with a simple configuration.

[Brief explanation of drawings]

Figure 1 is a diagram showing the configuration of the image information processing device, Figure 2 is a diagram showing the configuration of the CPU bus control logic controller, Figure 3 is a diagram showing the configuration of the image bus control logic controller, and Figure 4 is a diagram showing the configuration of the image data processing unit. 5 is a block diagram showing the structure of the address generation section, FIG. 6 is a block diagram showing the structure of the data processing section, and FIG. 7 is a block diagram showing the structure of the data processing section. Figure 8 is a diagram showing memory access in a 2-bank configuration, Figure 9 is a timing chart showing memory access in a 2-bank configuration, and Figure 10 is a diagram showing even-numbered memory banks in a 2-bank configuration. Figure 11 shows the access width control unit in a 2-bank configuration, and Figure 12 shows the memory in a 1-bank configuration. FIG. 13 is a timing chart showing memory access when 1 bank (J4) is configured, and FIG. 14 is a block diagram showing a configuration for generating a mask when 1 bank is configured. 1 ... CPU, 21 ... optical disk (storage medium),
23... Image scanner (input device), 24...
Image printer device (output device), 5o... memory (storage means), 51... address generation section (address generation means, switching means), 52... data processing section, 7...
... Adder (adding means), 8o... Selector (selecting means).

Claims (1)

[Scope of Claims] An image information processing device that stores image information input by an input device in a storage medium, and reads out and outputs the image information from the storage medium as needed, the access data width being N/ It consists of a first access unit which is 2 bits and a second access unit whose access data width is N/2 bits, and by accessing these first and second access units simultaneously, the access data width is N/2 bits. storage means for storing the image information as bits; address generation means for generating an address to be supplied to the storage means; addition means for incrementing the address generated by the address generation means; and access to the storage means. a switching means for switching between data access from 1 bit width to N/2 bit width and data access from N bit width; and a switching means for switching data access from 1 bit width to N/2 bit width. When switched, if the address generated by the address generation means specifies the first access unit, the address is supplied to the first and second access units, and the address generation means generates the address. If the address specifies the second access unit, the address is supplied to the second access unit, the address incremented by the addition means is supplied to the first access unit, and the switching means An image information processing apparatus comprising: control means for supplying addresses generated by the address generation means to the first and second access units when switching to bit width data access.