JPH0415879A - Raster arithmetic unit - Google Patents

Abstract

PURPOSE:To eliminate the need of rewriting pattern data when RAM is used and reducing the capacity of ROM when it is used by generating several patterns from one basic pattern by means of shifting an address. CONSTITUTION:A RAM part 101 storing pattern data, an address generator 102 generating the address corresponding pattern data to be accessed and a barrel shifter 103 which barrel-shifts pattern data that is read by the generated address are provided. Thus, pattern data which is integer-fold of or a one-to- integer of pattern data stored in the RAM part 101 is outputted by shifting the value of the address generated in the address generator 102. Thus, wasteful time required for rewriting pattern data can be eliminated when RAM is used for storing pattern data and the capacity of ROM can be reduced when it is used.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is used, for example, in an information processing device having an image editing function, and is capable of processing three types of data for source data, destination data, and pattern data. The present invention relates to a raster arithmetic device that performs term operations.

(Prior Art) In recent years, information processing devices that handle document images such as general documents and drawings have been actively developed. Such information processing devices are usually provided with a raster arithmetic device.

The raster arithmetic unit includes a logic arithmetic unit (hereinafter abbreviated as ALU), and stores, for example, pattern data (P) from a pattern RAM, source data (S) from a data processing unit, and data from a memory. This is to perform a ternary operation with the destination data (D) from the latch.

However, if the pattern data is stored in RAM in a raster arithmetic device used on a boat,
In order to obtain the required pattern data, the contents of the RAM must be rewritten, which has the drawback of being a waste of time.

Furthermore, in the case of a raster arithmetic device that stores pattern data in a ROM, it is necessary to store a plurality of pieces of data for one pattern, so there is a drawback that a large capacity is required.

(Problems to be Solved by the Invention) As described above, in conventional raster arithmetic devices, when RAM is used to store pattern data, it takes time to rewrite, and when ROM is used, It has the disadvantage of requiring a large capacity.

Therefore, this invention utilizes R for storing pattern data.
It is an object of the present invention to provide a raster arithmetic device which can eliminate wasted time required for rewriting pattern data when using an AM, and can reduce its capacity when using a ROM. The purpose is

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the raster arithmetic device of the present invention performs ternary arithmetic on three types of data including pattern data. A storage means for storing pattern data, an address generation means for generating an address corresponding to the pattern data to be accessed, and a shift means for barrel-shifting the read pattern data using the address generated by the address generation means. and configured to output pattern data that is an integer multiple or an integer fraction of the pattern data stored in the storage means by shifting the value of the address generated by the address generation means. There is.

(Function) This invention uses the above-described means to change the reading of pattern data, so it is possible to read pattern data that is an integral multiple or a fraction of an integral number without rewriting the pattern data or providing a plurality of pattern data. It is possible to output it.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 8 shows an example of an image storage/display/editing apparatus as an information processing apparatus according to the present invention.

In other words, this device controls each module.

Central processing unit (hereinafter abbreviated as CPU) that performs management and calculation processing 1, various external devices and program memory device
(MM) 3 or within the MMB, the direct memory access control unit (DM
A) 2. Hard disk device (external magnetic storage means)
A hard disk controller (HDC) 4 as the external device that controls the HD) 16, a floppy disk controller (FDC) 5 as the external device that controls the floppy disk device (FD) 17 that is an external magnetic storage means, and a user. A keyboard (KB) 18 is used for giving instructions to the device and inputting text, and a mouse (MO) is a pointing device for pointing a specific part of the screen displayed on the display, which will be described later.
) 19 and receives data, such as the peripheral input/output control unit (PIO) 6 as the external device is connected via the peripheral data input/output bus (P1O-BUS) 26, and the CPU , DMA 2 allows very high-speed data transfer.

In addition, the above CPUI, DMA2, MM3, P 10-B
US26, and system bus (SYS-BUS) 25
A CPU bus control logic controller (CBL) 7 is provided between the two. This CBL7 has data transfer of 5YS-
It is also possible to connect to other devices and control parts via BUS25.
It also controls the data bus and its arbitration so that they can be executed in parallel.

Furthermore, the 5YS-BUS 25 includes a communication processing control unit (COM) 8 for transmitting and receiving data with other external devices (not shown) via the communication line 20, and an external large-capacity storage means. An optical disk control unit (ODC) 9 that controls an optical disk device (OD) 21, this 5YS-B
The data bus and the Image bus control logic controller (IBL) 1-5 that controls the arbitration
is connected.

The C0M8 performs processing such as protocol control for data transmission and reception, and data bucketing and unpassocketing.

On the other hand, the IBL 15 includes a memory (DPM) 11 for storing image data, a linear density conversion process for image data, an image conversion process for enlarging/reducing conversion, or an encoding/compounding process for image data compression/expansion processing. an image processing unit (IPR) 12 that performs conversion processing, and an image data input/output bus (I1O-BUS) 27
is connected.

The DPMI 1 has a function not only as a memory for simply storing image data, but also various drawing functions. In addition, this DPMII includes a CRT display unit (CRT) 2 that uses a part of the DPMI 1 as a display.
A display control unit (CRTC) 10 for displaying on the 2nd screen is also connected.

The CRTC 10 has a function of reading display data from the display area of the DPMII in which a dual port memory device is used and sending it to the CRT 22 together with a synchronizing signal.

The above 110-BUS27 is connected to an image scanner device (SC) that reads image data from paper etc. and inputs it.
A scanner control unit (SCC) 13 controls the image printer (SCC) 23 and transfers data to the DPMI 1, reads data from the DPMII, and transfers it to the image printer device (
Printer control unit (PRC) 1 that controls printing on paper by transferring data to PRN) 24;
4 are connected, enabling high-speed data transfer.

FIG. 9 schematically shows the circuit configuration of the CBL 7 and its peripheral circuitry.

The CBL 7 includes an exclusive control unit (ARBT) 30 that performs access control and gate control based on the request signal 31 from the CPU 1 and the I) MA 2, and six gates 32.
．． It is composed of...

That is, CPUI, 5YS-BUS 25, PIO-
A gate 32°... is provided between BUS26 and MM3, and furthermore, DMA2 and 5YS-BUS25, PIO-B
Gates 32, . . . are provided between US26 and MM3. Therefore, unless CPU1 and DMA2 access the same bus or memory at the same time, ARB
Parallel operation is possible by controlling T30. For example, if the CPUI connects to the DP via 5YS-BUS25
At the same time as accessing Mll, DMA2 can write data from HD16 to MM3 via PIO-BUS26. Also, for example, if the same bus or memory is accessed at the same time, the ARBT30 will perform either CPUI or DMA2 processing first, and after that processing is completed, the other processing will be performed. There is.

FIG. 10 schematically shows the IBL 15 and its peripheral circuit configuration.

IBL15 is 5YS-BUS25.110BUS27
, the linear density conversion processing unit (LDC) 34 of the IPR 12 and the encoding/compounding conversion processing unit (C
an exclusive control unit (ARBT) 33 that performs access control and gate control based on a request signal from the ODEC) 35;
7 gates 36. It is composed of...

That is, this IBL15 is capable of various operations and parallel operations on image data, for example, 5CN2.
While writing the data read by B into the DPMI 1 at the same size, it is possible to write the linear density-converted data to the DPMI 1 via the LCD 34. However, in this case, the ARB 73 is not operated completely simultaneously, but by each request signal.
Arbitration is performed in step 3.

In addition, when request signals are sent from multiple master devices at the same time, the ARBT33 controls the processing of the request signals and also controls the gates 36° to avoid deadlock and operate simultaneously in parallel. is intended to be carried out if possible.

FIG. 11 shows the configuration of the DPMI 1 in detail.

In this DPMI 1, the memory 50 is a display memory (
It consists of two parts: a DM) 50a and a page memory (PM) 50b, each of which stores image data and code data. Here, DM50
A dual port memory is used as B, and the video data is read out from the serial port and sent to the CRT22.
It is now displayed in . On the other hand, a general-purpose DRAM is used for the PM 50b, so that it can be treated as a one-dimensional memory.

Further, the memory 50 has a two-bank configuration, and E
It is divided into VEN bank and ODD bank.

The address generation unit 51 generates an address for accessing the memory 50. This address generation section 51
has four independent two-dimensional address generators (AG), and is also capable of selectively outputting the address from the CPU 1 mentioned above.

The latch circuits 56 and 61 each have an address generating section 51.
A flip-flop for latching the ODD bank address of the memory 50 among the addresses from the EVE
It is composed of flip-flops for latching the addresses of N banks.

The data processing unit (raster arithmetic unit) 52 performs scaling, 3
Data processing such as term operations and clipping can be performed, and at this time, data from 1 to 3 from any pit address can be
It is possible to process 2-bit or 64-bit data.

The sequencer 53 includes an address generator 51 and a pig processor 5.
2, and the RAS signal and CAS that control the memory 50.
It has a function of generating control signals during memory access of the memory control unit 54, which generates a signal, an OE multiplied signal, a WE multiplied signal, and the like.

The display address output from the CRTC 10 mentioned above is
The selectors 57 and 58 select the address from the address generator 51 and input it to the memory 50.

Also, the address from the CRTC 10 is the cursor control unit 5.
The cursor is displayed at an appropriate position on the CRT 22 by comparing it with preset cursor position information. Furthermore, CRTCIO's H8YN
The C signal and the VSYNC signal are
Used as a synchronization signal.

The shift register 59 is a dual port memory (DM5
This converts the display data read from 0a) into serial data.

The synthesizing section 60 synthesizes the display data from the dual port memory and the cursor data from the cursor control section 55, and displays the data on the CRT 22.

FIG. 12 shows the configuration of the data processing section 52 in detail.

That is, the latch 88 temporarily stores data read from the memory 50.

The pattern RAM 86 stores patterns to be drawn in the memory 50.

The data processing unit 85 includes a flip-flop for temporarily storing data, a barrel shifter that shifts data according to an offset address, an enlargement/reduction conversion processing section that performs enlargement/reduction conversion processing, and an inversion process that inverts LSB-MSB of data. (none of which are shown).

ALU (logical operation unit) 87 performs a ternary operation, that is, pattern data (P) from pattern RAM 86, source data (S) from data processing unit 85, and data from latch 88 storing data from memory 50. A ternary operation is performed with the destination data (D).

Next, the operation of the above-mentioned DPMI 1 will be explained in detail including the peripheral hardware.

When accessing the memory 50 of the DPMI 1, all access requests are output to the ARBT 3B of the IBL 15. Then, in the ARBT 33, by performing arbitration, when a plurality of access requests occur, one access request is selected and processed.

Once the access is determined by ARBT3B, the sequencer code is provided to sequencer 53 in DPMI I. When the sequencer 53 starts operating, the memory 50 and the like are controlled.

In this embodiment, there are four types of access to DPMll. In other words, 10 accesses from 5CN2B and PRN24, and CP
CPU access from U1 and IPR1
These are raster processing access when image processing is performed using 2, and internal access which is access within DPMll.

Each access will be explained individually below.

First, regarding image input from 5CN2B in IO access, parameters are set for each related module by the CPU. At this time, one address generator (AG) in the address generation section 51 is used to generate an address to the memory 50.

That is, when 5CN23 starts operating, the read data is sent to 5CC13.

In 5CC13, this data is converted to the data bus width of ll0-BUS27. Then, a request to write data to DPMI 1 is issued to ARBT 33 .

The ARBT 33 receives this request, and if no other access request has been received, the gate 36. ... is controlled,
As a result, 5C sent from Ilo-BUS27
Data read by 5CN23 from C13 is DPM
Output to I1. At the same time, a sequencer code is sent to the sequencer 53.

Then, the sequencer 53 starts writing data to the memory 50 in the DPMI I. In this case, the address generator 51 selects the corresponding address, switches it to the ODD address and the EVEN address, and latches it into the respective latches 56 and 61. Then, by selecting the address from the latch 56.61 by the selector 57.58, the memory 50.
is input. On the other hand, the data is written into the memory 50 after being subjected to data processing in the data processing section 52. At this time, a control signal for the memory 50 is generated by the memory control section 54.

When data writing is thus completed, the sequencer 53 outputs an end signal to the ARBT 33, and further, the ARBT 33 outputs an end signal to the 5CC 13, thereby ending one data transfer.

2, the input operation from the 5CN 23 is completed by repeating the above operation and storing the image data for one sheet read from the 5CN 23 in the memory 50.

On the other hand, regarding image output to the PRN 24 during process 0 access, parameters are set for each related module by the CPU.

At this time, one AG in the address generation section 51 is used to generate an address to the memory 50.

That is, when PRN24 starts operating, PRC14
A request to read image data from the DPMI 1 is issued to the ARBT 33 via the 11O-BUS 27. Upon receiving this, the ARB 73B receives the access request from the gate 36. ... is controlled, and at the same time a sequencer code is sent to the sequencer 53.

As a result, the sequencer 53 starts reading out image data from the memory 50 in the DPMll.

In this case, the address generating section 51 selects the corresponding address, switches it to the ODD address, ):VEN address, and latches it into the respective latches 56 and 61. Then, the addresses from the latches 56 and 61 are input to the memory 50 by being selected by the selectors 57 and 58.

Further, the control signal for the memory 50 is transmitted to the memory control unit 54.
The image data is read out from the memory 50 by being generated from the image data. The read image data is subjected to data processing, that is, shift processing, mask processing, etc., in the data processing section 52, and then is processed by the gate 36. ... is output to ll0-BUS27. At this time, the sequencer 53 outputs an end signal to the ARB 73B, and the ARBT 3B further outputs an end signal to the PR014 to notify that the reading of image data has ended. Then, the PRC 14 receives and receives the image data, and further outputs it to the PRN 24, thereby completing one data transfer.

In this way, by repeating the above operations to read one sheet of image data from the memory 50 and outputting it to the PRN 24, the output operation to the PRN 24 is completed.

Next, CPU access will be explained.

From the CPUI, ARB is sent via 5YS-BUS25.
A read or write access request to the memory 50 of the DPM 11 is issued at 73B. In response to this request, in the ARBT 33, if there is no other access request to DPMI 1 or if it is selected by the arbiter, control is performed on the gate 36°, and furthermore, the CPU access to the sequencer 53 is performed. The sequencer code is output. Upon receiving this, the sequencer 53 starts accessing the memory 50.

In other words, the address from CPU1 is 5YS-BUS
25 to the address generating section 51 of the DPMll. This address is input to the memory 50 via selectors 57 and 58 in the address generator 51. In the case of reading, data is read out from the memory 50 by a control signal from the memory control unit 54,
Data processing section 52, gate 36...5YS-BU
It is sent to the CPUI via S25.

Also, in the case of writing, the data from the CPUI is 5
YS-BUS25, gate 36. ...Data processing section 5
2 to the memory 50. At this time, although the data width of the memory 50 is 64 bits wide, the data processing unit 52 selects data based on the lower bits of the address, thereby accessing the corresponding data. Note that writing is achieved by controlling write enable (WE) by the memory control unit 54.

Next, regarding raster processing access, here IPR
The case where image reduction processing is performed using No. 12 will be described as an example.

First, the CPU 1 sets parameters for each module to be used. In the case of this embodiment, after the image data read from the memory 50 is reduced by the LDC 34, the reduced image data is written to another address in the memory 50 again, so that the address generation Two AGs in section 51 are used.

That is, when processing starts, first A is sent from the LDC 34.
A request to read image data from the memory 50 is issued to the RBT 33 . If you accept this, ARBT3
3 outputs a sequencer code for external read access to the sequencer 53, thereby reading image data from the memory 50. This read image data is processed by the data processing section 52, the gate 36. LD via...
The read operation is completed manually by C34. At this time, the address on the source side of the two AGs is used. This readout operation is performed over several lines of the image, and is stored in a line buffer provided inside the LDC 34 for interpolation processing.

When an appropriate amount of image data is stored in the line buffer of the LDC 34, a write request or ARB is sent from the LDC 34.
It is output to T33. From ARBT33 who received this,
A write operation is started by outputting a sequencer code for external write access to the sequencer 53. In this case, by selecting the destination address of the address generator 51, the reduced image data output from the LDC 34 is transmitted to the gate 36. ...
The data is written to this address in the memory 50 via the data processing section 52.

The operation is completed by performing the above processing for one image.

Next, internal access within the DP-M 11 will be explained.

Regarding this internal access, there are several types of accesses, such as copy access to copy data to another address,
Swap access is used to exchange data, and drawing access is used to draw patterns. These accesses are
All controlled by sequencer 53 within DPMI I. Also, the address at this time is the address generator 51
For copy access and swap access, two AGs are used.

When the access mode is set in the internal sequencer inside the sequencer 53, an internal access request is issued to the ARBT 33. As a result, when the ARBT 3B accepts an internal access, the sequencer code is output to the sequencer 53. And this sequencer 33
The address of the address generator 51 is used to generate the memory 5.
o is accessed, and the data processing unit 52 processes the data. Note that the address generation unit 51 is capable of generating not only addresses of a simple rectangular area, but also affine transformation addresses such as rotation, trapezoidal addresses, etc., and it is also possible to perform copy access using these. Ru.

Next, the gist of the invention will be further explained.

FIG. 1 shows the structure of the pattern RAM 86.

That is, the RAM section 101 has 32 bits x 32 wor
It has an SRAM of 3.3 MHz and has a function of switching between CPU read/write and pattern read.

An address generator (ADG) 102 generates an X address XA and a Y address YA corresponding to an access pattern.

The barrel shifter (BS) 103, for example, as shown in FIG.
3 are connected to each other, and the 3
The pattern data (P) of 2b it is transferred to the above ADG1.
It is shifted according to the X address XA from 02.

The output selector 104 is configured as shown in FIG. 3, for example, and selects the pattern shifted at B5103 in accordance with the pattern magnification, and outputs it to the ALU 87 as a 64-bit pattern.

FIG. 4 shows the configuration of the RAM section 101.

That is, SRAMI 11 is 32b i tx32
I am serving W Or d capacity.

The CPU access counter 112 is a 5-bit O counter, and is incremented by one each time the CPU accesses the CPU.

The selector 113 switches between a read/write operation from the CPU 1 and a normal pattern read operation using a C10 signal. For example, when the C10 signal is "0",
The address of the SRAMI 11 is switched to the CPU access counter 112 side (the output of the access counter 112 is selected), and thereby CPU read/write is performed. Also, when the C10 signal is “1”, SRAMI
The address No. 11 is switched to the X address XA from the ADG 102, thereby performing a pattern read operation.

FIG. 5 shows the configuration of the ADG 102 described above.

That is, the gate 121 gates the address signal XST in response to the switching signal A/R.
2 gates the address signal YST in accordance with the switching signal A/R.

The adder 123 adds the output of the gate 122 and the address signal YAD.

The selectors 124 and 125 are connected to the gate 121, respectively.
The output of the adder 123 or the address of the adder 123 is used as pattern data (
).

For example, in the same magnification mode (×1), only the lower 5 bits of the 6-bit address are output. In addition, in double mode (x2), 6 bits each for X and Y
5bit with the address of t shifted 1 bit to the LSB side
It is designed to output t. Furthermore, in the 1/2x mode (X 1/2), the 6-bit addresses for each of X and Y are shifted by 1 bit toward the MSB side, and the lower 5 bits thereof are output.

EX-OR circuits 126 and 127 each have selector 1
24, 125 output and direction control signals XDIR, YDIR
This is the exclusive OR of the

The address signals XST and YST are the lower 6 bits of the start address of the drawing area, respectively, and the C
This is set in advance by the PUI.

The address signal YAD is the lower 6 bits of the Y address of the portion where a certain drawing operation is being performed, and is directly input from the outside.

The switching signal A/R is used to switch the pattern address between an absolute address and a relative address.

The direction control signals XDIR and YDIR are for controlling the direction of the pattern.

FIG. 6 is shown to explain the operations of absolute addressing and relative addressing.

That is, when the switching signal A/R is "0", the operation is performed using absolute addressing. In this case, gate 121,1
22 provides an address signal XST.

Since YST becomes "0', the output is XA=0°YA-Y
It becomes AD. As a result, a pattern as shown in FIG. 4(b) is applied to the basic pattern shown in FIG. 1(a). In this way, with absolute addressing, when the drawing area moves, the pattern changes according to the address. Therefore, this mode is advantageous for tiling processing.

On the other hand, when the switching signal A/R is "1", relative addressing is performed. The outputs in this case are XA-XST, YA-Y
It is ST+YAD. Therefore, as shown in FIG. 3(c), the pattern remains constant even if the drawing area moves.

FIG. 7 is shown to explain the relationship between the direction control signals XDIR to YDIR and the direction of the pattern.

That is, the direction control signal XDIR.

When both YDIRs are "0", the basic pattern is output as is, as shown in FIG.

Further, when the direction control signal XDIR is "1", the signal YD
When IR is "0", a pattern with left and right sides reversed is output as shown in FIG. 2(b).

Also, when the direction control signal XDIR is “0°”, the signal YD
When IR is "1", either a vertical or inverted pattern is output, as shown in FIG. 2(c).

Furthermore, when both the direction control signals XDIR and YDIR are "1", a pattern that is point symmetrical with respect to the basic pattern is output as shown in FIG.

In this way, four types of patterns can be generated from the same basic pattern, making it possible to efficiently store pattern data. Furthermore, when attempting to change a pattern, only the control signal level can be changed without reloading the entire pattern, thereby speeding up the processing.

Next, the operation when enlarging or reducing a pattern will be explained.

For example, assume that the same magnification mode (×1) is now set.

Then, from the selector 124125 of the ADC, 102,
Only the lower 5 bits of the 6-bit address are output. In this case, for example, input address r00,01.
~, 63'' is roo, 01 . ~,31,
00,01°~,31''. If you want, ALU8
7, a pattern of the same size is added.

Also, assume that the double mode (×2) is set, for example. Then, from the selectors 124 and 125, X, Y
5 bits obtained by shifting each 6-bit address by 1 bit toward the LSB side are output.

In this case, for example, the input address r00,01°~,6
3”, roo, 00,01°01, ~,31
．． 31J is output. In this way, each address is output twice, and the resulting pattern is also doubled. However, in this double mode, correct output cannot be obtained when the address signal XST is an odd number in the relative address. Therefore, in the output selector 104, 1 bit
Shifts and corrections are made.

Furthermore, assume that, for example, 1/2x mode (X 1/2) is set. Then, from the selectors 124 and 125, the address of 6 bits each for X and Y is transferred to the MSB side by 1 bit.
The lower 5 bits shifted by t are output. In this case, for example, input address rob, 01. ~, 63'', roo, 02, 04. ~, 30'' is output every other time. Therefore, a pattern 1/2 times as large as the basic pattern is obtained.

As described above, pattern data is enlarged or reduced by shifting addresses.

That is, by shifting the address of the pattern data to be accessed, a pattern that is an integral multiple or a fraction of the pattern data stored in the SRAM can be obtained. This makes it possible to generate a number of patterns from one basic pattern. Therefore, there is no need to rewrite the contents of the SRAM one by one, thereby speeding up the processing.

Although the above embodiments have been described using SRAM as an example, the present invention is not limited to this, and can also be applied to, for example, ROM. In this case, pattern data can be stored efficiently, so a ROM with a small capacity can be used.

It goes without saying that various other modifications can be made without departing from the gist of the invention.

[Effects of the Invention] As detailed above, according to the present invention, by shifting addresses, it is possible to generate a number of patterns from one basic pattern. If a RAM is used for the raster processing, it is possible to eliminate wasted time for rewriting pattern data, and if a ROM is used, a raster arithmetic device can be provided that can reduce its capacity.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram showing the configuration of a pattern RAM, FIG. 2 is a block diagram showing the configuration of a barrel shifter, and FIG. 3 is a block diagram showing the configuration of an output selector. , FIG. 4 is a block diagram showing the configuration of the RAM section, FIG. 5 is a block diagram showing the configuration of the address generator, and FIG. 6 is for explaining the operation when specifying absolute addressing and the operation when specifying relative addressing. 7 is a diagram showing an output example when the direction of a pattern is controlled. FIG. 8 is a block diagram showing the configuration of an image storage/display/editing device to which this invention is applied. FIG. 9 is a CPU A block diagram showing the configuration of the lotus control logic control unit and its surroundings, FIG. 10 is a block diagram showing the configuration of the lotus control logic control unit and its surroundings, FIG. 11 is a block diagram showing the configuration of the memory (DPM), FIG. 12 is a block diagram showing the configuration of the data processing section according to the present invention. 1...CPU (central processing unit) 2...DMA
(Direct memory access control unit) 3. MM (program memory device) 4... IDC (hard disk control unit), 5... FDC (floppy disk control unit)
, 6... PIO (peripheral input/output control unit) 7... CB
L (CPU lotus control logic control unit), 8...COM (communication processing control unit), 9...ODC (optical disk control unit)
10...CRTC (display control unit) 11...DP
M (memory) 12...IPR (image processing section),
13. 5CC (scanner control unit) 14...PR
C (printer control unit), 15...IBL (image bus control logic control unit), 16...HD (hard disk device), 17...FD (floppy disk device)
, 18...KB (keyboard) 19...MO(
Mouse) 20... Communication line, 21... OD (optical disk device), 22... CRT (CRT display unit) 2
3...5CN (scanner device) 24...PRN
(image printer device), 25...5YS-BUS
(System bus) 26...PIO-BUS (Peripheral data input/output bus), 27...I 1O-BUS
(image data input/output bus), 30.33...
ARBT (exclusive control unit) 32.36...gate,
34...LDC (cotton density conversion processing section), 35...C
0DEC (compression/expansion processing unit) 50...Memory, 51
. . . Address generation section, 52 . . . Data processing section, 53
...Sequencer, 54...Memory control unit, 55...
Cursor control unit, 56.61...Latch, 57.58
...Selector, 59...Shift register, 60...
-Synthesis unit, 85...Data processing unit, 86...
Pattern RAM, 87...ALU (logical operation unit),
88...Latch, 101...RAM section, 102...
・ADG (address generator) 103...BS (barrel shifter) 104...output selector, 111.
・・SRAM1112・・CPU access counter, 1
13...Selector, 121,122...Gate, 12
3... Adder, 124, 125. ...Selector, 1
26 127...EX-OR circuit. Applicant's representative Patent attorney Takehiko Suzue Diagram A/R, 0 (b) Diagram A/R: 1 (C) XDIR=YDIR, 0 (a) YDIR=0 (b) XDIR:YDIP=1 VDIP =1 (d) Diagram

Claims (1)

[Scope of Claim] A raster arithmetic device that performs a ternary operation on three types of data including pattern data, comprising: storage means for storing pattern data; and address generation means for generating an address corresponding to the pattern data to be accessed. and a shift means for barrel-shifting the read pattern data according to the address generated by the address generation means, and by shifting the value of the address generated by the address generation means, the storage means A raster arithmetic device characterized in that it outputs pattern data that is an integer multiple or an integer fraction of stored pattern data.