JPH0359878A - Sense amplifier driving circuit - Google Patents

Abstract

PURPOSE:To improve sense sensitivity by driving an output transistor by means of an intermediate potential between the output terminal of a P-type transistor and the output terminal of an N-type transistor and always holding the intermediate potential of both output terminals to be equal to the precharge potential of a bit line. CONSTITUTION:Output terminals 11 and 12 connected to the respectively common source nodes of N-type flip flops Q12 and Q16 and P-type flip flops Q11 and Q13 in a sense amplifier are connected in serial by first and second resistances R11 and R12, and the output terminals 11 and 12 are driven by the potential of the intermediate node 13 of the first and second resistances R11 and R12. Thus, two common source nodes of the flip flops of the sense amplifier can simultaneously be driven at the same speed, the deterioration of sensitivity owing to the variance of the capacity of the bit line is eliminated, and sense sensitivity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a sense amplifier drive circuit for a dynamic RAM having a CMOS-configured sense amplifier.

[Prior Art] A sense amplifier drive circuit and a sense amplifier of a conventional dynamic RAM are shown in FIGS. 4 and 5, respectively. The P-type transistor Q41 is a MOSFET driven to the power supply side, and has a source electrode connected to the power supply and a drain electrode serving as the output terminal 41.

N-type transistor Q42 is a MOSFE driven to the ground side.
At T, the source electrode is grounded and the drain electrode serves as the output terminal 42. FIG. 6 shows the drive signal φSE of the transistor Q41 and the drive signal φSE of the transistor Q42. Output terminal 41 is connected to a common source node 51 of the P-type transistors of the sense amplifier, and output terminal 42 is connected to a common source node 52 of the N-type transistors of the sense amplifier.

The output terminals 41 and 42 are precharged to an intermediate potential between the power supply and GND. After the signal in the memory cell appears on the bit line, it is output to the output terminal 4 by the N-type sense amplifier drive signal φSE and the P-type sense amplifier drive signal φ system.
The common source node 51 of the P-type transistor of the flip-flop connected to 1 is driven to the power supply side, and the output terminal 42
The common source node 52 of the N-type transistor of the flip-flop connected to is driven to the GND side.

“Optimiz” by Ra1ner Kraus et al.
ed Sensing Scheme.

f DRAMs” rsymposium onV
LSI C1rcuits Digest.

f Technical papers, p77-
78; According to Aug, 1988J, if the threshold voltage and conductance of the transistors constituting the flip-flop are set to the same values for both P-type and N-type, and the common source nodes of the flip-flops are driven simultaneously and at the same speed, the bit line Sensitivity deterioration due to capacitance variations can be ignored, so sensing sensitivity and sensing speed are greatly improved.
The through current flowing from the power supply to GND during the sensing operation is also reduced. Conventional sense amplifiers drive the common source nodes of flip-flops simultaneously and at the same speed, so the sense amplifier drive circuit is designed so that the conductance of the drive transistor is equal for P-type and N-type, and φS
The E signal and φ system are manually operated almost at the same time.

[Problems to be Solved by the Invention] It is difficult to drive two types of transistors at the same time by generating φSE and φ system signals with opposite phases using a delay circuit, etc. The characteristics of an N-type transistor have elements that vary independently during manufacturing, and even if the design conditions are the same, the same conditions cannot always be maintained due to manufacturing variations.

For this reason, the conventional sense amplifier drive circuit, in which the speed of driving the common source node of the sense amplifier is proportional to the conductance of the P-type and N-type transistors, has the disadvantage that sensitivity deterioration due to variations in bit line capacitance cannot be ignored. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a sense amplifier drive circuit that can drive two common source nodes of a flip-flop of a sense amplifier simultaneously and at the same speed, thereby achieving a significant improvement in sense sensitivity. .

[Differences between the invention and the prior art] In contrast to the conventional sense amplifier drive circuit described above, the present invention drives the output transistor with an intermediate potential between the output terminal of the P-type transistor and the output terminal of the N-type transistor, and The difference is that the device is designed to operate with the intermediate potential of the terminal always kept equal to the precharge potential of the bit line.

[Means for Solving the Problems] A sense amplifier drive circuit of the present invention is a sense amplifier drive circuit for a dynamic RAM having a sense amplifier using cross-connected flip-flops having a CMOS configuration. , the output terminals connected to the common source node of each of the P-type flip-flops are connected in series with the first and second resistors, and the first output terminal is driven by the potential of the intermediate node between the first and second resistors. It is characterized by In other words, the sense amplifier drive circuit of the present invention divides the resistance between the output terminal of the P-type output transistor and the output terminal of the N-type output transistor by a sufficiently large resistance that the current can be ignored, and generates an intermediate potential. By controlling the conductance of the output transistor using this signal, negative feedback is applied to the output signal so that the intermediate potential between both output terminals during operation is always equal to the precharge potential of the bit line. . Therefore, if the output potentials of the P-type and N-type output transistors are Vl and V2, respectively, and the precharge potential of the bit line is VP, the relationship of Vl-VP=VP-V2 is maintained, so Vl is the power supply potential, ■2 is GND
ia, and the second flip-flop of the sense amplifier
Two common source nodes can be driven simultaneously and at the same speed.

[Example code] FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In the figure, Qll, Q13 are P-type transistors, Q12
．． Q14-Q16 are N-type transistors, R11, R12
is resistance. Two resistors R11 and R are connected between the drain of the P-type transistor Qll whose source is connected to the power supply and the train of the N-type transistor Q12 whose source is grounded.
12 are connected in series, and the connection point 11 between Qll and R11 and the connection point 12 between Q12 and R12 serve as output terminals, respectively. The connection point 13 between R11 and R12 is N
P-type transistor Qll through type transistor Q14
and the drain of P-type transistor Q13. Furthermore, the connection point 13 is an N-type transistor Q15.
The gate of the N-type transistor Q12 and the drain of the N-type transistor Q16 are also connected through the gate. However, in order to suppress the through current flowing through the resistors R11 and R12, the resistance values of R11 and R12 are set to be sufficiently large.

Gate of P-type transistor Q13, N-type transistor Q
FIG. 2 shows temporal changes in the signals φPC and φS inputted to the gates of transistors Q16 and φSE inputted to the common gate of N-type transistors Q14 and Q015. Transistor Q14. Q10 is in the off state, transistors Q13. Q16 is in oscillation state, transistor Q
The gate of the transistor Q12 is fixed to the power supply potential, the gate of the transistor Q12 is fixed to the GND potential, and the potential of the output terminal 11 is Vll.
The potential V12 of the output terminal 12 is precharged to the precharge potential VP of the bit line. Signal φPC,
After the gates of transistors Qll and Q12 are separated from the power supply and GND by the φ scale, the signal φS is
E causes transistor Q14. When Q15 turns on, the gate of transistor QIL Q12 is connected to terminal 13.
connected to. If resistors R11 and R12 are made to have the same resistance value and transistors Qll and Q12 are made to have the same conductance, the potential difference between terminals 11 and 12 will expand while the potential of terminal 13 remains at the center value of the potentials of output terminals 11 and 12. . In other words, in the 1/2 VCC method, the output terminals 11.12
The output potential Vll, V12 is V11-VP=
While maintaining the VP-V 12(7) relationship, Vll approaches the power supply potential and V12 approaches the GND potential. Also, resistor R11
, R12, and the conductance of transistors Qll and Q12, the output potentials V11 and V12 are hardly affected because negative feedback is applied.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

In the figure, Q31. Q33 is a P-type transistor, Q32
．． Q34 to Q36 are N-type transistors, R31, R
32 is a resistance. Two resistors R31 are connected between the drain of the P-type transistor Q31 whose source is connected to the power supply and the train of the N-type transistor Q32 whose source is grounded.
, R32 are connected in series, and a connection point 31 between Q31 and R31 and a connection point 32 between Q32 and R32 each serve as an output terminal. Connection point 33 between R31 and R32
is connected to the positive phase input terminal of the differential amplifier circuit, the negative phase input terminal of the differential amplifier circuit is fixed to the bit line precharge potential VP, and the output side terminal 34 is connected to the P It is connected to the gate of the P-type transistor Q31 and the drain of the P-type transistor Q33. Also, terminal 34
is also connected to the gate of N-type transistor Q32 and the drain of N-type transistor Q36 through N-type transistor Q35. The source of P-type transistor Q33 is connected to the power supply, and the source of N-type transistor Q36 is grounded. However, in order to suppress the through current flowing through the resistors R31 and R32, the resistance values of R31 and R32 are set to be sufficiently large. FIG. 2 shows the temporal changes in the signals φPC and φR applied to the gate of the P-type transistor Q33 and the gate of the N-type transistor Q34, and the signal φSE applied to the common gate of the N-type transistors Q34 and 035. Warning transistor Q34. Q3
5 is in the off state, transistors Q33 and Q36 are in the on state, and the gate of the transistor Q31 is at the power supply potential.
The gate of the transistor Q32 is fixed to GND, and the potential V31 of the output terminal 31 and the potential V32 of the output terminal 32 are precharged to the precharge potential VP of the bit line. Transistor Q3L by signal φPC9φrC
After the gates of transistors Q32 are disconnected from the power supply GND, the signal φSE causes transistors Q34. Q
When transistors Q31.35 are turned on, transistors Q31.35 are turned on. The gate of Q32 is connected to the output side of the differential amplifier circuit. If the amplification factor of the differential amplifier circuit is sufficient, when the potential V33 of the terminal 33 is higher than VP, the potential V34 on the output side rises to near the power supply potential, and the potential V33 falls. On the other hand, VB2 is VP
When it is lower, V34 drops to near the GND potential and VB
The potential of 2 increases. Therefore, V33 is always equal to VP, and in order to make resistors R31 and R32 have the same resistance value, transistors Q31, Q32. Q34. Regardless of the ability of Q35, the output potential V31.32 of the output terminals 31.32.
VB2 approaches the power supply potential and VB2 approaches the GND potential while maintaining the relationship of VB2-VP=VP-VB2.

C Effect of the Invention] As explained above, the present invention always sets the intermediate potential between the potential of the output terminal that drives the sense amplifier toward the power supply side and the potential of the output terminal that drives the sense amplifier toward the GND side to be the precharge potential of the bit line. By driving the sense amplifier while maintaining the value of , the two common source nodes of the flip-flop of the sense amplifier can be driven simultaneously and at the same speed. Therefore, deterioration in sensitivity due to variations in bit line capacitance is eliminated, and the sense sensitivity is significantly improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
A waveform diagram of the signal manually input to the circuit shown in FIG.
3 is a circuit diagram of a second embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional sense amplifier drive circuit, FIG. 5 is a circuit diagram of a sense amplifier, and FIG. 6 is a circuit diagram of the circuit shown in FIG. 4. FIG. Qll, Q13. Q31. Q33゜Q41
．． Q51. Q52...P-type transistor, Q10. 014~Q 16°Q32. Q34~Q36゜Q53. Q54. Q42...N-type transistor, R11°R12°R31°R32... Resistor, If, 12. 31゜32.41.42...Output terminal, 51゜52 - Flip-flop common source node.

Claims (1)

[Claims] In a sense amplifier drive circuit for a dynamic RAM having a sense amplifier using cross-connected flip-flops in a CMOS configuration, the output terminal connected to the common source node of each of the N-type flip-flop and P-type flip-flop of the sense amplifier is 1. A sense amplifier drive circuit, characterized in that a first and second resistor are connected in series, and a first output terminal is driven by a potential at an intermediate node between the first and second resistors.