JPH0359891A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To speed up a reading speed by providing a resistance element in parallel with a first resistance between the drains of field effective transistors and the input of a sense amplifier circuit and controlling a first resistance value. CONSTITUTION:A control signal generation part 109 and a source are respectively connected to a digit line 120, and a control circuit 110 in which the resistance value between the plural field effective transistors Q1-Q3 whose drains are connected to the input of the sense amplifier circuit 107, and the input of the sense amplifier circuit is set to be variable is provided. Thus, the excess rise of a voltage in a node SA can be prevented by laying a resistance R2 whose resistance value comes to R1<R2 as against the sense amplifier input parasitic resistance R1 of a read circuit, and the voltage of the node SA speedily changes from 'off' to 'on' even if an on-bit is continuously selected. Thus, the reading speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a read method for a semiconductor memory device that requires high speed.

[Prior Art and its Problems] A reading method for a conventional semiconductor memory device will be described with reference to the drawings. FIG. 3-1 shows a schematic configuration of a first conventional readout circuit, and FIG. 3-2 is a detailed circuit diagram of the first conventional readout circuit. This will be explained below using FIG. 3-2. Although only an arbitrarily selected 1-bit memory element Ml is illustrated to simplify the explanation,
A plurality of memory elements are arranged in a matrix in the memory cell array section 105, and a 1-bit memory element is electrically connected to one digit line and one word line selected from the plurality of lines. Of course it is selected.

During writing, the memory element has two types of threshold voltages, for example, VTL,
One of the VTHs is set. If the gate voltage of the selected storage element at the time of reading is called VG, then V
The threshold voltage is set to satisfy the relationship TL<VG<VTH.

Now, if the threshold voltage of the selected memory element M1 is V, M1 becomes conductive and the voltage at the node SA drops (hereinafter,
This phenomenon is called discharge, and Ml at this time is called on-pit).

On the other hand, if the threshold voltage of Ml is the VT value, Ml becomes non-conductive and the voltage at the node SA increases (hereinafter, this phenomenon will be referred to as charge-up, and Ml at this time will be referred to as an off-pit).

Thereafter, the sense amplifier 107 amplifies the voltage change at the node SA and drives the output buffer to obtain data output.

Regarding the read mode, see Figures 1-3 (A) and (B).
shows the read mode input/output waveforms. There are various read modes depending on the measurement timing of the read speed, but TCE and TACC are illustrated here.

Next, a change in voltage at the sense amplifier manual node SA when reading is performed by changing the mode from TCE (charge up) to TACC (discharge) will be described.

The read mode input/output waveforms in FIG. 1-4(A) show voltage changes at the node SA in the first conventional example. Mode TC
The read speed by E (charge up) and TACC (discharge) are TCEI and T, respectively.
It is written as ACCI.

Note that when the input signal i is at a high level (MHI), it is called standby mode, and the digit line 12D at this time is either high impedance or grounded (grounded) by circuit means.
GND) potential.

On the other hand, the sense amplifier input node SA is also at high impedance or at GND potential. Here, a case will be described in which the node SA is at the GND potential in standby mode.

Now, reading is started by switching the input signal ττ from the high level (VIH) to the low level (VIL) in FIG. 1-4 (A). The voltage at node SA is GND
The potential rises from the potential to the set value VSA (on) when selecting the on-pit, and further rises to the set value VSA (off) when selecting the off-pit, and becomes stable.

If on-pit is selected by continuously switching the address input signal (TACC (discharge))
The voltage at node SA changes from VSA (off) to VSA (on)
It descends to and stabilizes.

However, in reading from the conventional semiconductor memory device described above, in the TCE (charge-up) mode, the voltage at the sense amplifier manual node SA actually begins to rise from the GND potential, exceeds the set value VSA (off), and VSA
(Off) There is a tendency to reach 2.

Next, the voltage change at the node SA in the second conventional example is shown in the input/output waveforms in the read mode in FIG. 1-4(B). T
TACC after CE (charge up) mode
When reading in (discharge) mode,
The voltage of contact SA is from VSA (off) 2 to VSA (off)
Then, it descends to VSA (on). In other words, TACC2 (discharge) in the second conventional example
In addition to the TACCI (discharge) read speed mentioned above, it also takes time for the voltage at the node SA to change from VSA (off) 2 to VSA (off), so the read speed is significantly slow. There is.

Although not shown in the figure, in the TACC%- code, the conventional semiconductor memory device is provided with a circuit that sets unselected digit lines to the GND potential. In the TACC mode, when an off-pit is selected by switching the Y address, the voltage of the selected digit line increases from the GND potential, and there is a strong tendency for the voltage at the sense amplifier input node SA to increase excessively.

Hereinafter, the read speed when on-pit is selected continuously is the same as TACC2 in FIG. 1-4 (B), so the explanation will be omitted.

As explained above, in conventional semiconductor memory devices, when an off-pit is selected, the voltage at the node SA tends to rise excessively, and when an on-pit is subsequently selected, the read speed is slow. It has the disadvantage of not being suitable.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a plurality of memory elements, a plurality of digit lines each connected to the drain of the memory element, and a sense amplifier circuit that detects a change in the digit line voltage. and a plurality of field effect transistors each having a source connected to the digit line and a drain commonly connected to the input of the sense amplifier circuit, and a resistance value between the field effect transistor and the input of the sense amplifier circuit being variable. It has a control circuit.

[Differences between the invention and the prior art] In contrast to the conventional semiconductor memory device described above, the present invention has a control signal generation section 109 and a control circuit 110, so that the resistance value of the input of the sense amplifier circuit can be adjusted according to the read mode. The difference is that it can be selected arbitrarily.

[Example code] Embodiments of the present invention will be described with reference to the drawings.

Note that the same components as the conventional example are denoted by the same reference numerals.

It will be described using the name and the explanation will be omitted.

FIG. 1-1 shows a block diagram of a readout circuit according to a first embodiment of the present invention. FIGS. 1-2 show a circuit diagram of a readout circuit according to a first embodiment of the present invention. This embodiment will be described below using FIGS. 1-2. Control signal creation unit 109
By controlling the signal S1 from the 1st to the VCC level (hereinafter referred to as "Htt") and the signal 7 to the GND level (hereinafter referred to as "L"), the transistor Q1 becomes conductive and the transistor Q2 becomes non-conductive. The circuit of FIG. 2 realizes the same function as the conventional circuit of FIG. 3-2. Therefore, as mentioned above, in TCE (charge up) mode,
The voltage at the sense amplifier human power node SA tends to rise excessively. Therefore, in this embodiment, in order to prevent an excessive voltage rise at this node SA, in the TCE mode, S1
By applying ="L $9 1= (4H"),
Transistor Q1 is rendered non-conductive and transistor Q2 is rendered conductive.

Here, the resistor R2 is designed so that its resistance value is R1<R2 with respect to the sense amplifier human parasitic resistance R1.
By using R2 having a large resistance value, it is possible to prevent an excessive voltage rise at the node SA.

Therefore, the speed of TACC2 (discharge) is improved.

Fig. 1-5A shows a control signal generation section, and Fig. 1-5B shows an example of input/output timing of control signals. Only in TCE mode, through resistor R2, in other read modes,
The other one is advantageous because the delay time required for the voltage change at the node SA to change through R1 having a small resistance value is small.

The effects of this embodiment are shown in FIG. 1-4 (A). Note that the present embodiment is shown as if it were the same as the first conventional example in the figure, but this is because in the first conventional example, the voltage at the node SA is excessive in the TCE (charge-up) mode. This is because it means an ideal state in which the value does not increase and is stabilized at the set value VSA (off).

However, strictly speaking, the resistance value R is higher than that of the conventional example.
2, the read speed of the TCE may be somewhat slower in this embodiment.

Furthermore, when arranging the control circuit 110, an increase in the delay time due to an increase in the parasitic capacitance of the sense amplifier input can be considered, but the read speed is significantly slower than in other read modes, and the maximum read speed of the semiconductor memory device is It is important to improve the speed of TACC (discharge) after TCE (charge up), which is the value.

FIG. 2-1 is a block diagram of a readout circuit according to a second embodiment of the present invention. In the T ACC mode, the control signal generation unit 209 detects that the Y address has been switched, and sets the control signal S1 to "L + y" and the correction to "H". The configuration of the creation section is shown, and an example of the human output timing of the control signal is shown in FIG. 2-2B.

In this embodiment, as in the first embodiment described above, the sense amplifier input resistance can be set according to the read mode, and an excessive rise in the voltage at the node SA at the time of off-pit selection can be prevented. Hereinafter, the read speed when on-pit is selected successively is the same as TACCI in FIG. 1-4 (A), so the explanation will be omitted.

[Effects of the Invention] As explained above, the present invention arbitrarily selects the resistance value of the sense amplifier input according to the read mode, thereby reducing the sense amplifier input node S that occurs when selecting an off-pit.
Excessive voltage rise of A can be prevented.

Therefore, even if you continue to select on-pit, the node SA
Since the voltage changes from VSA (off) to VSA (on) quickly (compared to the second conventional example shown in Figure 1-4 (B)), it is applicable to semiconductor memory devices that require high speed performance. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1-1 is a block diagram showing a readout circuit according to a first embodiment of the present invention. 101...Address buffer circuit, 102.
...... i-buffer circuit, 103...◆...◆
X-decoder circuit, 104...Y-decoder circuit, 105...◆...Memory cell array section, 10
6...Y-selector section, 107...
・Sense amplifier circuit, 108... Output buffer 7 circuit, 109... Control signal generation section, 110
・・・・・・Control circuit. 1-2 are circuit diagrams showing a readout circuit according to a first embodiment of the present invention. Ql-Q3...First to third field effect transistors (N-channel enhancement), Ml... Memory element, R1... Sense amplifier Input parasitic resistance (first resistance), R2... Resistance (second resistance), Sl...
......First control signal, n II It @
11 @ 11111111 Second control signal, SA...
...Sense amplifier human power node, 120...
...Digital line, 121...Word line. Figures 1-3 (A) and (B) are waveform diagrams showing input and output waveforms in the read mode; Figures 1-4 (A) are waveform diagrams showing input and output waveforms in the read mode of the first embodiment; 1-4
Figure (B) is a waveform diagram showing input and output waveforms in the read mode of the second conventional example, Figure 1-5A is a block diagram of the control signal generation section of the first embodiment, and Figure 1-5B is the waveform diagram of the first embodiment. FIG. 3 is a waveform diagram showing an example control signal output timing. 2nd-
FIG. 1 is a block diagram showing a readout circuit in a second embodiment of the present invention. 209... Control signal generation unit, Fig. 2-2A is a block diagram showing the control signal generation unit of the second embodiment, the second
-2B is a waveform diagram showing the control signal output timing of the second embodiment, Fig. 3-1 is a block diagram showing the readout circuit of the first conventional example, and Fig. 3-2 is a waveform diagram of the first conventional example. FIG. 3 is a circuit diagram showing a readout circuit.

Claims (1)

[Scope of Claims] A plurality of memory elements, a plurality of digit lines each connected to the drain of the memory element, a sense amplifier circuit for detecting a change in voltage of the digit line, and a sense amplifier circuit having a source connected to each of the digit lines. a plurality of field effect transistors that are connected together and whose drains are commonly connected to the input of the sense amplifier circuit, and a first resistor is connected between the drains of the field effect transistors and the input of the sense amplifier circuit. In the semiconductor memory device, the control circuit also receives at least one resistance element in parallel with the first resistor between the drain of the field effect transistor and the input of the sense amplifier circuit, and makes the resistance value of the first resistor variable. A semiconductor memory device comprising: