JPH0360077A - Insulated gate field effect transistor - Google Patents

Abstract

PURPOSE:To maintain a drain junction capacitance constant and to improve a cross modulation characteristic by forming the same conductivity type high impurity concentration buried layer as that of a substrate on a high impurity concentration region under the bottom of a drain region, and further providing higher impurity concentration third drain region than that of a second drain region connected to part of a channel region adjacent to the end of the second drain region. CONSTITUTION:B ions are selectively implanted to a P-type silicon substrate 1 to form a P<+> type buried region 2 having about 1X10<20>cm<-3>, and a P<-> type epitaxial layer 3 having about 1X10<15>cm<-3> of impurity concentration is grown on the surface including the region 2. Then, P or As ions are selectively implanted to the layer 3 to form N<+> type first drain and source regions 4, 5 having about 1X10<18>cm<-3> of impurity concentration are formed. Then, the surface including the regions 4, 5 is thermally oxidized to form a silicon oxide film 6, P ions of high concentration are selectively implanted to form a N<+> type third drain region 9a on the layer 3 of the end of the second drain region forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor, and particularly to a dual gate type insulated gate field effect transistor.

[Conventional technology]

Insulated gate field effect transistors are used as high-frequency amplification elements in television tuners, and one of the reasons for this is that the input/output transfer characteristics are in principle very close to square-law characteristics, and most third-order or higher-order terms are As a result, the cross-modulation characteristics are excellent.

In recent years, there has been a trend to emphasize cross-modulation characteristics between adjacent channels in television broadcasting, and the advantages of insulated gate field effect transistors are becoming stronger.

FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional insulated gate field effect transistor.

As shown in FIG. 2, a P-type epitaxial layer 3 is provided on a p-type silicon substrate 1, and n-type high concentration impurities are selectively introduced into the surface of the epitaxial layer 3 to form a first drain region 4. and the first source region 5 is formed. Next, an oxide film 6 is provided over the entire surface, and first and second gate electrodes 7.8 are selectively provided on the oxide film 6 in a region between the drain region 4 and the source region 5. Next, using the gate electrodes 7 and 8 as a mask, n-type impurity ions are implanted into the second drain region 9 connected to the drain region 4, the second source region 10 connected to the source region 5, and the gate electrodes 7 and 8.
One island area is formed in the middle of the area. Next, PSG (Phospho) is applied to the surface including the gate electrode 7.8.
-8 ilicate glass) film 12 is deposited, selectively forming contact holes to form a drain electrode fi 13 connected to the drain region 4 and a source electrode 14 connected to the source region 5 to form an n-channel MO3 field effect transistor (hereinafter referred to as (referred to as n-channel MOSFET).

An n-channel MOSFET is generally used with its source grounded, and an input signal is applied to the first gate electrode 7, and the second gate electrode 8 is grounded at a high frequency. At the same time, by adjusting the bias applied to the second gate electrode 7, the drain current, that is, the mutual conductance of the first gate electrode 7, is varied, and the power gain is adjusted.

[Problem to be solved by the invention]

The conventional insulated gate field effect transistor described above inherently has the advantage of superior cross-modulation characteristics, but this also applies to the intrinsic device region, where It is not possible to suppress the spread of the formed depletion layer, and the drain capacitance fluctuates significantly due to bias, and as a result, a nonlinear part represented by junction capacitance is added as a parasitic element, resulting in cross-modulation. There is a problem that the characteristics deteriorate.

An object of the present invention is to provide an insulated gate field effect transistor that maintains a constant drain junction capacitance and has excellent cross modulation characteristics.

[Means to solve the problem]

The insulated gate field effect transistor of the present invention includes a buried layer with a high impurity concentration of one conductivity type provided on one main surface of a semiconductor substrate of a conductivity type, and a low impurity concentration buried layer of one conductivity type provided on the surface including the buried layer. an epitaxial layer with an impurity concentration; a first drain region and a first source region with a high impurity concentration of opposite conductivity type provided on the surface of the epitaxial layer; and a third drain region provided in a part of the channel forming region. , a gate electrode provided on the silicon oxide film provided on the surface including the first and third drain regions and the first source region; and a gate electrode provided on the surface of the epitaxial layer in alignment with the gate electrode. It has a second drain region connected to the first and third drain regions, and a second source region connected to the first source region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.

As shown in Figure 1, the impurity concentration is I x 1019C.
By selectively implanting boron ions into the surface of the p-type silicon substrate 1 of about I+"-',
A p+ type buried region 2 of about M-3 is formed, and a p-type epitaxial layer 3 with an impurity concentration of about I x 1015C11-3 is grown on the surface including the buried region 2.6 Next, the surface of the epitaxial layer 3 is grown. By selectively implanting phosphorus ions or arsenic ions into the
Next, the surface including the drain region 4 and source region 5 is thermally oxidized to form a silicon oxide film 6.
An n+ type third drain region 9a is formed on the surface of the epitaxial layer 3 at the tip of the second drain region formation region by selectively implanting phosphorus ions at a high concentration. next,
A first gate electrode 7 and a second gate electrode 8 are selectively formed on the surface of the silicon oxide film 6 in a region between the drain regions 4, 9a and the source region 5. Next, the gate electrode 7,
Using 8 as a mask, phosphorus ions are implanted to form a second drain region 9 that connects to the drain regions 4 and 9a, a second source region 1o that connects to the source region 5, and an island region 11, and stabilize the characteristics over the entire surface. A PSG film with one film length and two layers for the purpose of. Next, the PSG film 1 film length 2 oxide film 6 on the drain region 4 and source region 5 is selectively and sequentially etched to form a contact hole, and an aluminum layer is deposited on the surface including the contact hole. Selective etching is performed to form a drain electrode 13 connected to the drain region 4 of the contact hole and a source electrode 14 connected to the source region 5, respectively.

Here, since the impurity concentration of the drain region 4 and the drain region 9a is about three orders of magnitude higher than the impurity concentration of the epitaxial layer 3, the depletion layer mostly spreads toward the epitaxial layer 3 side, but the depletion layer spreads toward the p+ type buried layer 2. The thickness remains constant and stable against high-frequency fluctuations in the drain voltage. In other words, the drain capacitance takes a constant value with respect to the bias applied to the junction, and becomes a linear capacitance.
Cross-modulation characteristics are improved.

〔Effect of the invention〕

As explained above, in the present invention, a buried layer with a high impurity concentration of the same conductivity type as the semiconductor substrate (that is, a conductivity type opposite to that of the drain region) is formed in the high impurity concentration region below the bottom of the drain region, and a buried layer with a high impurity concentration is formed in the high impurity concentration region below the bottom of the drain region. By providing a third drain region connected to the second drain region in a part of the channel region adjacent to the tip of the drain region and having a higher impurity concentration than the second drain region, the junction parasitic capacitance caused by the drain voltage can be reduced. This has the effect that the spread can be significantly suppressed, and therefore, an insulated gate field effect transistor for high frequency bands with low distortion can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional insulated gate field effect transistor. 1...p type silicon substrate, 2...p+ type buried layer, 3
...p-type epitaxial layer, 4...first drain region, 5...first source region, 6...oxide film,
7... First gate electrode, 8... Second gate electrode, 9... Second drain region, 9a... Third drain region, 10... Second source region, 11... Island region, 12... PSG film, 13... Drain electrode, 14... Source electrode.

Claims (1)

[Claims] a buried layer with a high impurity concentration of one conductivity type provided on one main surface of a semiconductor substrate of one conductivity type; an epitaxial layer with a low impurity concentration of one conductivity type provided on the surface including the buried layer; a first drain region and a first source region of opposite conductivity type with high impurity concentration provided on the surface of the channel forming region, a third drain region provided in a part of the channel forming region, and the first and third drain regions. and a gate electrode provided on the silicon oxide film provided on the surface including the first source region, and a gate electrode provided on the surface of the epitaxial layer in alignment with the gate electrode and connected to the first and third drain regions. An insulated gate field effect transistor comprising: a second drain region connected to the first source region; and a second source region connected to the first source region.