JPH0360091A - Push-back method - Google Patents
Push-back methodInfo
- Publication number
- JPH0360091A JPH0360091A JP19487289A JP19487289A JPH0360091A JP H0360091 A JPH0360091 A JP H0360091A JP 19487289 A JP19487289 A JP 19487289A JP 19487289 A JP19487289 A JP 19487289A JP H0360091 A JPH0360091 A JP H0360091A
- Authority
- JP
- Japan
- Prior art keywords
- board
- printed circuit
- periphery
- boards
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 230000001846 repelling effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 11
- 238000005476 soldering Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野〕
本発明は、配線用プリント基板に部品を実装する際に複
数のプリント基板を同時に保持するプッシュバック工法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a pushback method for simultaneously holding a plurality of printed circuit boards when components are mounted on a wiring printed circuit board.
配線用プリント基板に部品を実装する際に、複数のプリ
ント基板を同時に保持する方法としてプッシュバンク工
法がある。When mounting components on printed circuit boards for wiring, there is a push bank method as a method for holding multiple printed circuit boards at the same time.
該方法を第2図、第3図(A)(B)に於いて略述する
。The method will be briefly described in FIGS. 2 and 3 (A) and (B).
複数枚(図では4枚)のプリント基板2を打抜き得る原
板1に予め配線パターンを形成し、又部品取付用の孔を
穿設しておき、次にプリント基板2を型3で打抜く(第
3図(A))、この打抜いた基板2を再度打抜いた孔に
強制的に嵌戻す。A wiring pattern is formed in advance on a base plate 1 from which a plurality of printed circuit boards 2 (four in the figure) can be punched, and holes for mounting parts are drilled, and then the printed circuit boards 2 are punched out using a die 3 ( In FIG. 3(A)), the punched substrate 2 is forcibly fitted back into the punched hole.
而して、原板1は複数枚のプリント基板2を保持した状
態となり、部品の挿入、ハンダ付等の部品実装に於いて
は、複数枚の基板2を一体的に処理できる。Thus, the original board 1 is in a state in which a plurality of printed circuit boards 2 are held, and the plurality of circuit boards 2 can be integrally processed during component mounting such as insertion of components and soldering.
斯かるプッシュバック工法の問題として、基板2を原板
1に強制的に嵌戻した際の基板2と原板1との間の反抗
によって原板1、基板2の全体に反り、歪が発生する。A problem with such a pushback method is that when the substrate 2 is forcibly fitted back onto the original plate 1, the resistance between the substrate 2 and the original plate 1 causes warping and distortion in the entire original plate 1 and substrate 2.
従来、この反り、歪を除去する方法としては、ホットプ
レスにより加圧、加熱して反り一歪を矯正していた。Conventionally, the method for removing warps and distortions has been to apply pressure and heat using a hot press to correct warps and distortions.
[発明が解決しようとする課題]
然し、上記した従来の矯正方法では、見がけ上反り、歪
が除去されただけであり、反り、歪の原因となる残留応
力が基板内に残置している。[Problems to be Solved by the Invention] However, in the conventional straightening method described above, only the apparent warping and distortion are removed, but residual stress that causes the warping and distortion remains in the substrate. .
この為、部品実装後ハンダ付工程のハンダ付、或は炉内
でのハンダ再溶融処理で加熱された場合、残留応力が解
放され、再び基板の反り、歪が発生する1部品実装後の
基板の反り、歪の発生は部品の破損や、部品のハンダ付
不良の原因となり、歩留りの低下、製品の信頼性の低下
を招いていた。For this reason, if the board is heated during soldering in the soldering process after component mounting or during solder remelting in a furnace, the residual stress will be released and the board will warp or distort again. The occurrence of warpage and distortion causes damage to parts and poor soldering of parts, leading to lower yields and lower product reliability.
本発明は、斯かる実情に鑑み、プツシユバツク工法に於
ける基板の反り、歪の発生を防止しようとするものであ
る。In view of these circumstances, the present invention aims to prevent the occurrence of warpage and distortion of the substrate in the pushback construction method.
[課題を解決するための手段]
本発明は、原板より複数の配線用プリント基板を打抜き
、更に嵌戻して、該複数の配線用プリント基板を保持す
るプッシュバック工法に於いて、原板のプリント基板部
分の周辺に沿って所要の孔を穿設することを特徴とする
ものである。[Means for Solving the Problems] The present invention provides a push-back method in which a plurality of printed circuit boards for wiring are punched out from an original board, and further fitted back to hold the plurality of printed circuit boards for wiring. The feature is that required holes are bored along the periphery of the part.
[作 用コ
プリント基板部分の周辺に沿って所要の孔を穿設するこ
とで、プリント基板部分の周辺部の剛性か小さくなり、
プリント基板を打抜き嵌戻した際に生じる歪を前記周辺
部が吸収して、原板、プリント基板に反り、歪が発生ず
るのを防止する。[Operation]By drilling the required holes along the periphery of the printed circuit board, the rigidity of the periphery of the printed circuit board is reduced,
The peripheral portion absorbs the distortion that occurs when the printed circuit board is punched out and refitted, thereby preventing warping and distortion in the original board and printed circuit board.
[実 施 例] 以下、図面を参照しつつ本発明の一実施例を説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
原板1に配線パターンを形成した後、基板部分の周囲に
各打抜線に沿って長孔4を穿設する。After forming a wiring pattern on the original board 1, long holes 4 are bored around the board portion along each punch line.
該長孔4の穿設により基板部分の周囲に剛性の小さい周
辺部5が形成される。By forming the elongated hole 4, a peripheral portion 5 having low rigidity is formed around the substrate portion.
而して、基板2を打抜き、更に嵌戻すと、打抜きの際に
生じる加工歪、更に嵌戻した際の原板1と基板2間の反
椀は、前記周辺部5か変形することで解放され、基板2
、原板1の反り、歪の発生が防止される。Therefore, when the substrate 2 is punched out and further fitted back, the processing strain caused during punching and the warp between the original plate 1 and the substrate 2 when fitted back are released by the deformation of the peripheral portion 5. , substrate 2
, warpage and distortion of the original plate 1 are prevented.
尚、上記実施例では打抜線に沿って長孔を穿設したが、
該打抜線に沿って丸孔を複数穿設してもよい。In addition, in the above embodiment, long holes were bored along the punching line, but
A plurality of round holes may be bored along the punch line.
[発明の効果]
以上述べた如く本発明によれば、プッシュバック工法に
於ける原板、基板の反り、歪の発生を防止することがで
き、実装部品の破損防止、実装精度の向上、ハンダ付の
信頼性の向上を図ることができ、歩留りの向上、製品品
質の向上に大きく寄与する。[Effects of the Invention] As described above, according to the present invention, it is possible to prevent warpage and distortion of the original plate and board in the pushback method, prevent damage to mounted components, improve mounting accuracy, and improve soldering. This will greatly contribute to improving yield and product quality.
第1図は本発明の一実株例の説明図、第2図、第3図(
A>(B)は従来例の説明図である。
1は原板、2は基板、3は型、4は長孔、5は周辺部を
示す。
特 許 出 願 人
国際電気株式会社Figure 1 is an explanatory diagram of an example of a plant of the present invention, Figures 2 and 3 (
A>(B) is an explanatory diagram of a conventional example. 1 is an original plate, 2 is a substrate, 3 is a mold, 4 is a long hole, and 5 is a peripheral portion. Patent application Hito Kokusai Electric Co., Ltd.
Claims (1)
嵌戻して、該複数の配線用プリント基板を保持するプッ
シュバック工法に於いて、原板のプリント基板部分の周
辺に沿って所要の孔を穿設することを特徴とするプッシ
ュバック工法。1) In the pushback method, in which a plurality of wiring printed circuit boards are punched out from an original board, and then fitted back together to hold the plurality of wiring printed circuit boards, required holes are punched along the periphery of the printed circuit board portion of the original board. The pushback method is characterized by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19487289A JPH0360091A (en) | 1989-07-27 | 1989-07-27 | Push-back method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19487289A JPH0360091A (en) | 1989-07-27 | 1989-07-27 | Push-back method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0360091A true JPH0360091A (en) | 1991-03-15 |
Family
ID=16331711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19487289A Pending JPH0360091A (en) | 1989-07-27 | 1989-07-27 | Push-back method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0360091A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58159392A (en) * | 1982-03-17 | 1983-09-21 | 日立化成工業株式会社 | Method of producing printed circuit board |
| JPS59215786A (en) * | 1983-05-24 | 1984-12-05 | 興亜電工株式会社 | Blank board for punching printed circuit board |
-
1989
- 1989-07-27 JP JP19487289A patent/JPH0360091A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58159392A (en) * | 1982-03-17 | 1983-09-21 | 日立化成工業株式会社 | Method of producing printed circuit board |
| JPS59215786A (en) * | 1983-05-24 | 1984-12-05 | 興亜電工株式会社 | Blank board for punching printed circuit board |
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