JPH0360106A - Laminated chip inductor - Google Patents

Laminated chip inductor

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Publication number
JPH0360106A
JPH0360106A JP19728889A JP19728889A JPH0360106A JP H0360106 A JPH0360106 A JP H0360106A JP 19728889 A JP19728889 A JP 19728889A JP 19728889 A JP19728889 A JP 19728889A JP H0360106 A JPH0360106 A JP H0360106A
Authority
JP
Japan
Prior art keywords
electrode
magnetic material
inductance elements
electrodes
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19728889A
Other languages
Japanese (ja)
Inventor
Haruhisa Isoda
磯田 治久
Satoshi Murata
諭 村田
Kikuo Wakino
喜久男 脇野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP19728889A priority Critical patent/JPH0360106A/en
Publication of JPH0360106A publication Critical patent/JPH0360106A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To avert the effect of static induction or electromagnetic induction between inductance elements vertically close to by a method wherein a substrate sheet on almost the whole surface on which an electrode is provided is laid between the inductance elements in laminated state and then the electrode is grounded. CONSTITUTION:A substrate sheet 8 is formed of a non-magnetic material or a magnetic material, as for the non-magnetic material, various ceramics are applicable while as for the magnetic material, a ferrite e.g. similar to the sheets 1-5 is applicable. Almost the whole surface of this sheet 8 leaving both ends wherein outer leading-out electrodes 10a, 11a are positioned is coated with a conductive paste to form an electrode 14 as shown shaded by oblique lines. Accordingly, inner electrodes 10, 11 fill the role of inductance elements; the electrode 14 is laid between the inner electrodes 10, 11 positioned vertically close to be grounded through an outer electrode 24 so that the effect of static induction may be averted. Furthermore, since the substrate sheet 8 is formed of the non-magnetic material, the effect of electromagnetic induction between the inner electrodes 10, 11 can be averted regardless of the existance of the electrode 14.

Description

【発明の詳細な説明】 本発明は、複数のインダクタンス素子を積層してチップ
構造とした積層チップインダクタに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer chip inductor having a chip structure by stacking a plurality of inductance elements.

差速!1すLと匡澹 従来、積層チップインダクタとしては、絶縁性磁性シー
ト上に内部電極をストレート状名はコイル状に設け、こ
のシートを複数枚積層したものが種々知られており、第
6図、第7図にその一例を示す。
Different speed! Conventionally, various types of multilayer chip inductors have been known in which internal electrodes are provided on an insulating magnetic sheet in the form of a straight or coiled shape, and a plurality of these sheets are laminated, as shown in Fig. 6. , an example is shown in FIG.

第6図において、1,3,4.5はフェライトグリーン
シートで、シート4,5上にはインダクタンス素子とし
て機能する内部電極10.10.11.11がitペー
ストの塗布にてストレートな形状に形成され、両端は外
部引出し電極10a、llaとされている。
In Figure 6, 1, 3, and 4.5 are ferrite green sheets, and on the sheets 4 and 5, internal electrodes 10, 10, 11, and 11 that function as inductance elements are made into straight shapes by applying IT paste. The external lead electrodes 10a and 10a are formed at both ends.

シート4,5は必要枚数のダミーシート3を介在させ、
さらにその上下にダミーシート1,2を重ねて加圧、積
層し、焼成する。その後、バレル研磨又は平面研磨を施
し、第7図に示す如く、両端に導電ペーストを塗布、焼
付けることで一対すつの外部電極20〜23を形成し、
積層チ・ノブインダクタとされる。
The sheets 4 and 5 are interposed with the required number of dummy sheets 3,
Further, dummy sheets 1 and 2 are stacked on top and bottom of the dummy sheets 1 and 2, and the dummy sheets are laminated under pressure and fired. After that, barrel polishing or surface polishing is performed, and as shown in FIG. 7, a pair of external electrodes 20 to 23 are formed by coating and baking a conductive paste on both ends.
It is considered to be a multilayer Chi-nobu inductor.

ところで、この種の積層チップインダクタでは、個々の
インダクタンス素子間の静電誘導及び電磁誘導の影響が
問題となり、同一シートに並設された内部電極10.1
0間及び11.11間は影響が出ない十分な間隔を設け
られるが、上下方向に近接する内部電極10.11間は
、第8図に示す距離a、bが問題となり、静電誘導及び
電磁誘導の影響がでる。
By the way, in this type of laminated chip inductor, the influence of electrostatic induction and electromagnetic induction between individual inductance elements becomes a problem, and internal electrodes 10.
0 and 11.11 can be provided with a sufficient distance without any influence, but between the internal electrodes 10.11 which are close to each other in the vertical direction, the distances a and b shown in Fig. 8 become a problem, and electrostatic induction and It is affected by electromagnetic induction.

距離a、bを大きくすることはチップ自体が大型化し、
しかも完全に影響を排除できることもなく、好ましい対
策ではない。
Increasing the distances a and b means that the chip itself becomes larger,
Moreover, it is not a desirable countermeasure because it cannot completely eliminate the effects.

そこで、本発明の課題は、積層チップインダクタにおい
て、前記距離a、bを必要以上に大きくすることなく、
上下方向に近接するインダクタンス素子間の静電誘導又
は電磁誘導の影響を排除することにある。
Therefore, an object of the present invention is to provide a multilayer chip inductor without making the distances a and b unnecessarily large.
The objective is to eliminate the influence of electrostatic induction or electromagnetic induction between vertically adjacent inductance elements.

課題を解決するための手段と作 以上の課題を達成するため、本発明に係る積層チップイ
ンダクタは、積層状態のインダクタンス素子の間に、ほ
ぼ全面に電極を設けた基材シートを介在させた。前記電
極をアースに落とすことにより、電極を挾んで近接する
インダクタンス素子間の静電誘導が防止される。また、
電極を設けた基材シートを非磁性材にて形成すれば、上
下方向に近接するインダクタンス素子間の電磁誘導も防
止される。一方、電極を設けずに非磁性シートのみを介
在させてもよく、この場合には上下方向に近接するイン
ダクタンス素子間の電磁誘導が防止される。
Means and Production for Solving the Problems In order to achieve the above-mentioned problems, the multilayer chip inductor according to the present invention has a base sheet provided with electrodes on almost the entire surface thereof, interposed between the laminated inductance elements. By grounding the electrode, electrostatic induction between adjacent inductance elements sandwiching the electrode is prevented. Also,
If the base sheet provided with the electrodes is made of a non-magnetic material, electromagnetic induction between vertically adjacent inductance elements can also be prevented. On the other hand, only a nonmagnetic sheet may be provided without providing an electrode, and in this case, electromagnetic induction between vertically adjacent inductance elements is prevented.

丈鳳獅 以下、本発明に係る積層チップインダクタの実施例につ
き、添付図面を参照して説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of a multilayer chip inductor according to the present invention will be described with reference to the accompanying drawings.

[第1実施例、第1図、第2図参照コ 第1図は積層前のインダクタの各要素を示し、基本的に
は第1図に示した従来の積層チップインダクタと同様の
要素から構成されている。
[See Embodiment 1, Figures 1 and 2] Figure 1 shows each element of the inductor before lamination, and is basically composed of the same elements as the conventional laminated chip inductor shown in Figure 1. has been done.

即ち、1〜5はフェライトグリーンシートで、フェライ
ト粉末、有機溶媒及びバインダ等を混練して泥しように
した後、押出し法、引上げ法又はブレード法等によりシ
ート状に成形したものである。これらの基材シートのう
ち、シート4,5上にはその表面にAg、Ag−Pd等
を含む導電ペーストが塗布され、インダクタンス素子と
しての内部電極10.10及び11.11が形成され、
両端には外部引出し電極10a、 llaが形成されて
いる。なお、内部電極10.11は互いに重なり合わな
いように形成されている。
That is, ferrite green sheets 1 to 5 are obtained by kneading ferrite powder, an organic solvent, a binder, etc. to form a slurry, and then forming the sheet into a sheet by an extrusion method, a pulling method, a blade method, or the like. Among these base sheets, a conductive paste containing Ag, Ag-Pd, etc. is applied to the surfaces of sheets 4 and 5, and internal electrodes 10.10 and 11.11 as inductance elements are formed.
External extraction electrodes 10a and lla are formed at both ends. Note that the internal electrodes 10 and 11 are formed so as not to overlap each other.

基材シート8はその目的によって非磁性材又は磁性材か
らなり、非磁性材としては例えば各種セラミックス、磁
性材としては例えばシート1〜5と同様のフェライトが
使用される。このシート8上には前記外部引出し電極I
Qa、llaが位置する両端部を残してほぼ全面に導電
ペーストが塗布され、斜線で示す電極14が形成されて
いる。
The base sheet 8 is made of a non-magnetic material or a magnetic material depending on its purpose, and the non-magnetic material is, for example, various ceramics, and the magnetic material is, for example, ferrite similar to the sheets 1 to 5. On this sheet 8, the external extraction electrode I
A conductive paste is applied to almost the entire surface except for both ends where Qa and lla are located, and electrodes 14 shown by diagonal lines are formed.

以上の構成からなるシート4,5をその間にシート8及
びダミーシート3.3さらに上下にダミーシート1,5
をそれぞれ必要枚数積み重ね、加圧する。実際の量産工
程では各シート4,5.8は多数の導体を印刷した幅広
のものを一度に積層し、第1図、第2図に示す1単位の
インダクタを構成するようにカットする。これを適当な
温度で焼成し、バレル研磨、平面研摩等を施した後、外
部に露出した外部引出し電極10a、lla及び電極1
4の両端部に対応する位置に導電ペーストを塗布、焼付
けし、外部電極20〜23及び接地用外部電極24を形
成する。
Sheet 8 and dummy sheet 3.3 and dummy sheets 1 and 5 above and below are placed between sheets 4 and 5 having the above configuration.
Stack the required number of each and apply pressure. In the actual mass production process, each sheet 4, 5.8 is a wide sheet printed with a large number of conductors, which are laminated at once and cut to form one unit of inductor as shown in FIGS. 1 and 2. After firing this at an appropriate temperature and performing barrel polishing, surface polishing, etc., the external lead electrodes 10a, lla and electrode 1 exposed to the outside are
A conductive paste is applied and baked at positions corresponding to both ends of 4 to form external electrodes 20 to 23 and a grounding external electrode 24.

以上の構成からなる積層チップインダクタにおいては、
内部電極10.10.11.11がインダクタンス素子
として機能し、上下に近接する内部電極10゜11間は
電極14が介在し、かつその外部電極24を通じてアー
スがとられることにより、静電誘導の影響が排除される
。また、基材シート8を非磁性材にて形成することによ
り、電極14の有無に関係なく、内部電極10.11間
における電磁誘導の影響が排除される。一方、基材シー
ト8を磁性材にて形成すれば、電極14の機能によって
静電誘導の影響のみが排除される。
In the multilayer chip inductor with the above configuration,
The internal electrodes 10.10.11.11 function as inductance elements, and the electrode 14 is interposed between the vertically adjacent internal electrodes 10 and 11, and grounding is established through the external electrode 24, thereby preventing electrostatic induction. influence is eliminated. Furthermore, by forming the base sheet 8 from a non-magnetic material, the influence of electromagnetic induction between the internal electrodes 10 and 11 is eliminated regardless of the presence or absence of the electrodes 14. On the other hand, if the base sheet 8 is made of a magnetic material, only the effects of electrostatic induction can be eliminated by the function of the electrodes 14.

[第2実施例、第3図〜第5図参照コ 本第2実施例の積層チップインダクタは、製品化される
最終形態として、第5図に示すように、インダクタンス
素子として機能する内部電極10〜13が一列に積層さ
れた状態となり、いわば第8図に示した距1Iibを0
としたものである。
[See Second Example, Figures 3 to 5] The multilayer chip inductor of this second example has an internal electrode 10 functioning as an inductance element, as shown in Figure 5, in its final form as a product. ~13 are stacked in a row, so to speak, the distance 1Iib shown in FIG.
That is.

その製作は、フェライトグリーンシート4〜7上にそれ
ぞれ内部電極10〜13を形成したもの、基材シート8
上の全面に斜線で示す電極14を形成したものを準備し
、これらを必要枚数のダミーシート3を介在させ、かつ
、上下にダミーシート1゜2を重ねて加圧する。その後
、第4図に一点鎖線で示すカット線にて、並置された各
内部電極10〜13が分離するように1単位のインダク
タにカットし、これを適当な温度で焼成する。さらに、
バレル研磨、平面研磨等を施した後、外部に露出した各
外部引出し電極10a〜13aごとに導電ペーストを塗
布、焼付けし、外部電極25〜28を形成する。同時に
外部に露出した各電極14の端部に跨って導電ペースト
を塗布、焼付けし、接地用外部電極29を形成する。
Its production consists of forming internal electrodes 10 to 13 on ferrite green sheets 4 to 7, respectively, and base material sheet 8.
An electrode 14 shown by diagonal lines is formed on the entire surface of the electrode, and a required number of dummy sheets 3 are interposed therebetween, and the dummy sheets 1.degree..2 are stacked one above the other and pressed. Thereafter, the inductor is cut into one unit along the cut line shown by the dashed line in FIG. 4 so that the internal electrodes 10 to 13 arranged in parallel are separated, and this is fired at an appropriate temperature. moreover,
After performing barrel polishing, surface polishing, etc., a conductive paste is applied and baked on each of the external extraction electrodes 10a to 13a exposed to the outside to form external electrodes 25 to 28. At the same time, a conductive paste is applied and baked across the ends of each electrode 14 exposed to the outside to form an external grounding electrode 29.

以上の構成において、電極14の機能及び基材シート8
(磁性材又は非磁性材)の機能については、前記第1実
施例での説明と同様であり、上下方向に近接する内部電
極10.11.12.13間での静電誘導及び電磁誘導
の影響が防止される。
In the above configuration, the function of the electrode 14 and the base sheet 8
The function of the (magnetic material or non-magnetic material) is the same as that described in the first embodiment, and electrostatic induction and electromagnetic induction between the internal electrodes 10, 11, 12, 13 that are close to each other in the vertical direction. Impact is prevented.

なお、本発明に係る積層チップインダクタは前記実施例
に限定するものではなく、その要旨の範囲内で種々に変
更できる。
Note that the multilayer chip inductor according to the present invention is not limited to the above-mentioned embodiments, and can be variously modified within the scope of the gist.

特に、一つのシート4〜7上に形成されるインダクタン
ス素子の数ないしは積層数は任意であり、コンデンサ素
子等と組み合わせた複合電子部品としてもよい、また、
第2実施例において、基材シート8上の電極14は第1
実施例と同様に両端部を残してほぼ全面に形成してもよ
い。
In particular, the number of inductance elements or the number of laminated layers formed on one sheet 4 to 7 is arbitrary, and it may be a composite electronic component combined with a capacitor element etc.
In the second embodiment, the electrode 14 on the base sheet 8 is
As in the embodiment, it may be formed over almost the entire surface, leaving both ends intact.

急豊曵羞玉 以上の説明で明らかなように、本発明によれば、積層状
態のインダクタンス素子の間にほぼ全面に電極を設けた
基材シートを介在させたため、該電極を挾んで近接する
インダクタンス素子間の静電誘導を防止でき、インダク
タンス素子間の距離を小さくでき、より小型化が可能と
なる。また、前記基材シートを非磁性材にて形成すれば
、それを挾んで近接するインダクタンス素子間の電磁誘
導を防止できる。
As is clear from the above explanation, according to the present invention, a base sheet having electrodes provided on almost the entire surface is interposed between the laminated inductance elements. Electrostatic induction between the inductance elements can be prevented, the distance between the inductance elements can be reduced, and further miniaturization is possible. Furthermore, if the base sheet is made of a non-magnetic material, electromagnetic induction between adjacent inductance elements can be prevented by sandwiching the base sheet.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1実施例であるインダクタの積層前
の分解斜視図、第2図は第1図のものを積層し、外部電
極を設けた状態での斜視図である。 第3図は本発明の第2実施例であるインダクタの積層前
の分解斜視図、第4図は第3図のものを積層した状態の
斜視図、第5図は第4図のものを1単位にカットし、外
部電極を設けた状態での斜視図である。第6図は従来の
インダクタの積層前の分解斜視図、第7図は第6図のも
のを積層し、外部電極を設けた状態での斜視図、第8図
は第7図のものの垂直断面図である。 1〜7・・・フェライトグリーンシート、8・・・基材
(磁性又は非磁性)シート1.10〜13・・・内部電
極(インダクタンス素子)、14・・・電極、20〜2
3 、25〜28・・・外部電極、24.29・・・接
地用外部電極。 第 1 図 第2図 第6図 第7図 第8図
FIG. 1 is an exploded perspective view of an inductor according to a first embodiment of the present invention before lamination, and FIG. 2 is a perspective view of the inductor shown in FIG. 1 laminated and provided with external electrodes. FIG. 3 is an exploded perspective view of an inductor according to a second embodiment of the present invention before lamination, FIG. 4 is a perspective view of the inductor in FIG. 3 in a laminated state, and FIG. It is a perspective view in a state cut into units and provided with external electrodes. Fig. 6 is an exploded perspective view of a conventional inductor before lamination, Fig. 7 is a perspective view of the inductor in Fig. 6 laminated and with external electrodes provided, and Fig. 8 is a vertical cross-section of the inductor in Fig. 7. It is a diagram. 1-7... Ferrite green sheet, 8... Base material (magnetic or non-magnetic) sheet 1.10-13... Internal electrode (inductance element), 14... Electrode, 20-2
3, 25-28...external electrode, 24.29... external electrode for grounding. Figure 1 Figure 2 Figure 6 Figure 7 Figure 8

Claims (3)

【特許請求の範囲】[Claims] 1.インダクタンス素子を設けた基材シートを積層して
なる積層チップインダクタにおいて、ほぼ全面に電極を
設けた基材シートを、積層状態のインダクタンス素子の
間に介在させ、前記電極に接地用の外部電極を取り付け
たことを特徴とする積層チップインダクタ。
1. In a multilayer chip inductor formed by laminating base sheets provided with inductance elements, a base sheet provided with electrodes on almost the entire surface is interposed between the laminated inductance elements, and an external electrode for grounding is attached to the electrode. A multilayer chip inductor characterized in that it is attached.
2.前記電極が設けられている基材シートが非磁性材か
らなることを特徴とする請求項1記載の積層チップイン
ダクタ。
2. The multilayer chip inductor according to claim 1, wherein the base sheet on which the electrodes are provided is made of a non-magnetic material.
3.インダクタンス素子を設けた基材シートを積層して
なる積層チップインダクタにおいて、非磁性シートを積
層状態のインダクタンス素子の間に介在させたことを特
徴とする積層チップインダクタ。
3. A multilayer chip inductor formed by laminating base sheets provided with inductance elements, characterized in that a nonmagnetic sheet is interposed between the laminated inductance elements.
JP19728889A 1989-07-28 1989-07-28 Laminated chip inductor Pending JPH0360106A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19728889A JPH0360106A (en) 1989-07-28 1989-07-28 Laminated chip inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19728889A JPH0360106A (en) 1989-07-28 1989-07-28 Laminated chip inductor

Publications (1)

Publication Number Publication Date
JPH0360106A true JPH0360106A (en) 1991-03-15

Family

ID=16371972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19728889A Pending JPH0360106A (en) 1989-07-28 1989-07-28 Laminated chip inductor

Country Status (1)

Country Link
JP (1) JPH0360106A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0515409U (en) * 1991-07-31 1993-02-26 京セラ株式会社 Laminated coil
JPH0523513U (en) * 1991-08-31 1993-03-26 太陽誘電株式会社 Multilayer inductance component
JPH06302436A (en) * 1993-04-12 1994-10-28 Tdk Corp Stacked noise absorbing element composite
JP2012156192A (en) * 2011-01-24 2012-08-16 Tdk Corp Laminated electronic component and mounting structure for electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115813A (en) * 1985-11-15 1987-05-27 Matsushita Electric Ind Co Ltd Shielded device
JPS63268297A (en) * 1987-04-24 1988-11-04 Matsushita Electric Ind Co Ltd high frequency circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115813A (en) * 1985-11-15 1987-05-27 Matsushita Electric Ind Co Ltd Shielded device
JPS63268297A (en) * 1987-04-24 1988-11-04 Matsushita Electric Ind Co Ltd high frequency circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0515409U (en) * 1991-07-31 1993-02-26 京セラ株式会社 Laminated coil
JPH0523513U (en) * 1991-08-31 1993-03-26 太陽誘電株式会社 Multilayer inductance component
JPH06302436A (en) * 1993-04-12 1994-10-28 Tdk Corp Stacked noise absorbing element composite
JP2012156192A (en) * 2011-01-24 2012-08-16 Tdk Corp Laminated electronic component and mounting structure for electronic component

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