JPH0360143A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit in which a plurality of logic circuits are formed on the same wafer. Regarding WSi.

[Conventional technology]

The conventional WSi is Nikkei Electronics 1987.6.
As described in No. 1 No. 422 P141 to P161 "Possibilities and Limitations of Wafer Scale LSi", the repeating logic circuits are made rectangular, and the intervals between the rectangular logic circuits are left. This interval between the logic circuits was used as a wiring area between the logic circuits.

[Problem to be solved by the invention]

In the above conventional technology, since the shape of the repeating logic circuit is rectangular, if you try to connect the logic circuits without leaving any gaps between them, the four logic circuits on the top, bottom, left, and right that touch the four sides of the logic circuit of interest are connected. In order to connect more logic circuits, it is necessary to widen the space between logic circuits and use this space as a wiring area to connect multiple logic circuits. Integration efficiency decreases.
In addition, there is a problem in that the wiring length becomes long and signal delay becomes large.

An object of the present invention is to realize WSi without reducing the integration efficiency of logic circuits and without increasing signal delay.

[Means to solve the problem]

For the above purpose, the shape of the repeating logic circuit is a regular hexagon,
By providing signal terminals on six sides of the regular hexagon, arranging the logic circuits with the minimum required distance between them, and wiring between each logic circuit between adjacent logic circuits. achieved.

[For production]

Since the shapes of the logic circuits that are repeatedly arranged are regular hexagons of the same size, the logic circuits can be integrated over the entire wafer surface without any spacing unless there is a wiring factor.

Moreover, by making the shape of the integrated circuit a regular hexagon,
There are six adjacent logic circuits, and the mutual wiring between the six logic circuits is shortened, so that signal delay can be minimized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a plurality of repeating logic circuits 2 on a wafer 1.
FIG. 2 is an enlarged view of seven adjacent logic circuits in FIG. 1. Note that the same numbers shown in FIGS. 1 and 2 indicate the same parts.

A plurality of regular hexagonal logic circuits 2 are regularly arranged on the wafer 1, and the intervals between the logic circuits 2 are set to the minimum necessary interval. The signal terminal 3 of the logic circuit 2 is connected to each side of the logic circuit 2 (
6 sides), and mutual signals are exchanged between adjacent logic circuits 2 through the signal terminals 3.

According to the present invention, the shape of the logic circuit 2 is a regular hexagon and signal terminals are provided on each side, so that six adjacent logic circuits can be connected without reducing the degree of integration of the logic circuit formed on the wafer. This has the effect of allowing the shortest connection between logic circuits.

Although this embodiment has been explained with signal connections only between adjacent logic circuits, by widening the interval between logic circuits and using the expanded area as a wiring area, logic circuits other than the adjacent logic circuits can be connected. It is clear that signals can be connected to both, and even in this case, the degree of integration does not decrease compared to the conventional rectangular logic circuit system.

〔Effect of the invention〕

According to the present invention, six logic circuits can be connected to one logic circuit in the shortest possible time, and the shape of the logic circuit is a regular hexagon, so that a large number of logic circuits can be connected on one wafer without reducing the degree of integration of the logic circuits. This has the effect of allowing the integration of logic circuits.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of logic circuits on a wafer according to an embodiment of the present invention, and FIG. 2 is an enlarged view of seven adjacent logic circuits among the logic circuits shown in FIG. 1... Wafer, 2... Logic circuit, 3... Signal terminal. 4+, Kijin Patent Attorney 11) Kawasuo ≧= Banquet! Figure diagram

Claims (1)

[Claims] 1. In wafer scale LSi (WSi) in which multiple logic circuits are integrated on one wafer, the shape of the logic circuits is a regular hexagon, the logic circuits are arranged regularly on the wafer, and the logic circuits are arranged regularly on the wafer. A semiconductor integrated circuit characterized in that signal terminals are provided on six sides of the circuit, and the logic circuits are interconnected by the signal terminals.