JPH0360169A - Thin film transistor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistor memories.

[Conventional technology]

Recently, E2FR that can be written/erased/read electrically
As a memory such as OM, a thin film transistor memory in which a memory element is formed of a thin film transistor is considered.

FIG. 11 is a circuit diagram of a conventional thin film transistor memory, in which T1 is a memory thin film transistor (hereinafter referred to as a memory transistor), and T2 is each memory transistor T.
1. Selection thin film transistors (hereinafter referred to as selection transistors) are provided in series to correspond to the selection transistors 1 and 1, respectively. The source electrode S of the selection transistor T2 is connected to the drain electrode of the memory transistor T1 paired with it, and the pair of memory transistors T2 connected to each other are
1 and the selection transistor T2 constitute one memory element M, respectively. In addition, GLI and GL2 are a pair of gate lines (address lines), and SL and DL are source and drain lines (data lines).
The gate lines GLI and GL2 and the source and drain lines SL and DL are arranged in a matrix so as to be orthogonal to each other. The memory element M has gate lines GLI and GL2 and source and drain lines S.
The gate electrode G of the memory transistor T1 is connected to the first gate line GL1 of the pair of gate lines GLI and GL2, and the gate electrode G of the selection transistor T2 is connected to the first gate line GL1 of the pair of gate lines GLI and GL2. It is connected to the second gate line GL2. Further, the source electrode S of the memory transistor T1 is connected to the source line SL, and the drain electrode of the selection transistor T2 is connected to the drain line DL.

Writing, erasing, and reading from this thin film transistor memory are performed as follows.

In FIG. 11, (a) shows the state of voltage application during writing, (b) shows the state of voltage application during erasing, and (c) shows the state of voltage application during reading. Note that (a), (b), and (c) all show the state when one memory element M at the upper left in the figure is selected.

First, writing will be explained. During writing, as shown in FIG. 11(a), the selected first and second gate lines GL1. A positive voltage +1/2 corresponding to 1/2 of the write/erase voltage vP of the memory transistor T1 is applied to GL2, respectively.
V P and the on-voltage V of the selection transistor T2. applying N (e.g. +10v) and selecting a source;
A negative voltage -1/2Vp corresponding to 1/2 of the write/erase voltage VP is applied to the drain lines SL and DL, respectively, and the unselected first gate line GLI and source.

The potential of the drain lines SL and DL is 0 (ground), and the potential of the unselected second gate line GL2 is V. P.

(for example, OV). Note that the memory transistor T1
For example, when the write/erase voltage V is 40V, "1
/2V p +20V --1/2V P l;!
-20V There is. When we apply such a voltage signal,
The selection transistor T2 of the memory element (hereinafter referred to as selected memory element) M located at the intersection of the selected gate line GLI, GL2 and the source, drain line SL, DL is turned on, and the gate, source, and drain of the memory transistor T1 are turned on. A potential difference corresponding to the write/erase voltage VP between
A potential difference between +1/2Vp and -1/2Vp is generated, and the memory transistor T1 enters the write state. In addition,
In other memory elements (hereinafter referred to as non-selected memory elements) M on the selected gate lines GLI and GL2, the potential difference that occurs between the gate, source, and drain of the memory transistor T1 is only 1/2 V p, This memory transistor T1 is therefore in a write inhibited state.

Also, the gate line GLI is not selected.

Regarding the memory elements on GL2, the memory element at the lower left in the figure has a potential difference of only 1/2 Vp between the gate, source, and drain of the memory transistor T1, similar to the non-selected memory element M. This memory transistor T1 is therefore in a write inhibited state. Furthermore, regarding the memory element at the lower right in the figure, the potential generated between the gate, source, and drain of the memory transistor T1 is 0 (no voltage applied), similar to the non-selected memory element M described above. That is, the gate, source, and drain are at equal potential, and therefore this memory transistor T1 is also in a write inhibited state.

Further, during erasing, as shown in FIG. 11(b), the first and second gate lines GLI are selected.

G L 2 += 'ctL tL - 1/2V p,
Source and drain lines SL are selected depending on the voltage applied to the VoN.

+1/2Vp is applied to each DL. Note that unselected gate lines GL1. GL2 and source.

The signals applied to the drain lines SL and DL are the same as in the above writing. When such a voltage signal is applied, an opposite potential difference corresponding to the write/erase voltage V is generated between the gate, source, and drain of the memory transistor T1 of the selected memory element M, and the voltage is held in the memory transistor T1. data will be deleted. Again, the gate and source of the memorized transistor T1 of the unselected memory element M.

The potential difference generated between the memory transistor T1 and the drain is only 1/2Vp, and the memory transistor T1 is in an erase inhibited state.

On the other hand, during reading, as shown in FIG. 11(c), the first and second gate lines GLI are selected.

VSI for each GL2! At the same time, VD is applied to the drain line DL of the selected source and drain lines SL and DL, and the potential of the source line SL is set to O. Note that the above V SEL and VD are the write/erase voltage Vp (
40V), for example, V SFI
+, -0V, and VD-10V.

Also, during this reading, unselected gate lines GLI,
The signals applied to GL2 and the source and drain lines SL and DL are the same as those during writing and erasing. When such a voltage signal is applied, a current flows from the drain line DL to the source line SL in accordance with the data held in the memory transistor T1 of the selected memory element M.
This is output as read data.

In addition, in any of the above write, erase, and read operations, the voltage applied to the selected source and drain lines SL and DL is also applied to the unselected memory elements M on the source and drain lines SL and DL. However, the gate potential of the selection transistor T2 of this unselected memory element M is V. ,.

Since it is in the off state, the unselected memory element M
The memory transistor T1 is not affected by the applied voltage. That is, the selection transistor T2 not only selects the memory transistor T1, but also functions as a guard transistor that guards the memory transistor T1 from the voltage applied when it is not selected.

[Problem to be solved by the invention]

However, the conventional thin film transistor memory described above is
Since only one selection transistor T2 is provided for the memory transistor T1, if the selection transistor T2 has a characteristic defect, the memory transistor T1 selected by the selection transistor T2 is selected and guarded. The problem was that reliability was low because it was impossible to do so. Moreover, in the conventional thin film transistor memory described above, a gate voltage is applied to the same gate electrode G of the memory transistor T1 during writing and erasing as well as during reading. There is also a problem in that the threshold voltage changes, and as a result, when the number of readings exceeds several thousand, stable reading becomes impossible.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a thin film transistor memory that can significantly improve reliability and perform semi-permanently stable reading. There is a particular thing.

[Means to solve the problem]

In order to achieve the above object, the thin film transistor memory of the present invention provides a thin film transistor for selection in series on both sides of the thin film transistor for memory, and a thin film transistor for memory and a thin film transistor for selection located on the side opposite to their gate electrodes. In addition, a second gate electrode for reading is provided facing the semiconductor layer with a gate insulating film having no charge storage function interposed therebetween.

[For production]

That is, in the thin film transistor memory of the present invention, the selection thin film transistor is provided in series on both sides of the memory thin film transistor, and the selection thin film transistor is provided with a second gate electrode for reading, so that writing and erasing can be performed with the selection thin film transistor. This is done by applying a gate voltage to the original gate/membrane electrode of the thin film transistor for memory, and reading is done by applying a gate voltage to the second gate electrode of the thin film transistor for selection and the thin film transistor for memory. According to thin film transistor memory, even if the characteristics of one selection thin film transistor are poor, the other selection thin film transistor can be used to select and guard the selection thin film transistor, which can significantly improve reliability. In addition, if reading is performed by applying a gate voltage to the second gate electrode of the selection thin film transistor and the memory thin film transistor, a gate that changes the threshold voltage of this transistor is applied to the original gate electrode of the memory thin film transistor at the time of reading. Since there is no need to apply a voltage, it is possible to eliminate changes in the threshold voltage of the memory thin film transistor due to repeated reading and to perform stable reading semi-permanently.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 8 show a first embodiment of the present invention.

First, to explain the basic configuration of the thin film transistor memory of this embodiment, Fig. 1 is a circuit diagram of the thin film transistor memory. A pair of selection thin film transistors (hereinafter referred to as selection transistors) are provided in correspondence with each other. This pair of selection transistors 720a.

T20b is provided on both sides of the memory transistor TIO. In addition, the above-mentioned moly transistor T
IO and a pair of selection transistors 720a.

T20b respectively uses its original gate electrode Ga as a write/erase gate electrode, and has a readout second gate electrode (
The structure includes a readout gate electrode (hereinafter referred to as a readout gate electrode) Gb. Then, the pair of selection transistors T20
a, one selection thin film transistor T of T20b
20a connects its source electrode S to a memory transistor T.
The other selection thin film transistor T20b has its drain electrode integrated with the source electrode S of the memory transistor TIO, and is connected in series with the memory transistor TlO. By means of memory transistor TIO
This pair of selection transistors T20a, T20b and the memory transistor T20a and T20b are connected in series to each other.
One memory element M is constituted by IG.

In addition, GLa is a write/erase gate line (address line), GLb is a read gate line (address line), and SL and DL are source and drain lines (
data line) and both gate lines GLa.

GLb and the source and drain lines SL and DL are arranged in a matrix so as to be orthogonal to each other. and,
The memory element M has gate lines GLa and GLb and source and drain lines SL.

A memory transistor TIO and a dual selection transistor T20a are respectively arranged at the intersection with DL.

The write/erase gate electrode Ga of T20b is connected to a common write/erase gate line GLa, and is connected to the memory transistor TIO and both selection transistors 720a.

The read gate electrode Gb of T2Qb is connected to the common read gate line GLb. Further, the drain electrode of one selection transistor T20a of the memory element M is connected to the drain line DL, and the source electrode S of the other selection transistor T20b is connected to the source line SL.

Writing, erasing, and reading from this thin film transistor memory are performed as follows.

In FIG. 1, (a) is when writing, (b) is when erasing,
(c) shows the voltage application state during reading. In addition,
(a), (b), and (c) all show the state when one memory element M in the upper left corner of the figure is selected.

First, to explain about writing, when writing, Figure 1 (
As shown in a), the selected gate lines GLa, GL
The write/erase voltage vp of the memory transistor TIO (for example, 40
+1/2Vp (“2
0v) is applied L, the potential of the read gate line GLb is set to O (ground), and the write/erase voltages V,
-1/2V p (-20
) is applied to the unselected gate lines GLa, G
Lb and source.

The potentials of the drain lines SL and DL are set to O. When such a voltage signal is applied, the selected gate line GL
a, the selection transistor 720 of the selection memory element M located at the intersection of GLb and the source and drain lines SL and DL;
a, T20b is turned on by applying a voltage to the write/erase gate electrode Ga, and a potential difference corresponding to the write/erase voltage V is created between the write/erase gate electrode Ga and the source/drain electrodes S, D of the memory transistor TIO. arise,
This memory transistor TIO enters the write state. Furthermore, in other unselected memory elements M on the selected gate lines GLa and GLb, the memory transistor TIO
and selection transistor T20a.

Gate electrode Ga and source for writing and erasing T20b.

The potential difference between the drain electrodes S and D is only 1/2V P, so this memory transistor TIO is in a write inhibited state. Furthermore, regarding the memory elements on the unselected gate lines GLa and GLb, the memory element at the lower left in the figure is connected to the write/erase gate electrode Ga of the memory transistor T20, similarly to the unselected memory element M above.
and sauce.

The potential difference between the drain electrodes S and D is 1/2Vp.
, and therefore this memory transistor TIO
is in a write-blocked state. Furthermore, regarding the memory element at the lower right of the figure, similarly to the unselected memory element M, the write/erase gate electrode G of the memory transistor TIO is
The potential generated between a and the source and drain electrodes S and D is O (i pressure not applied). i.e. gate and source,
The potential is equal between the memory transistor TIO and the drain, so this memory transistor TIO is also in a write inhibited state.

Furthermore, during erasing, as shown in FIG. 1(b), 1/2V is applied to the write/erase gate line GLa of the gate lines GLa and GLb to be selected, and the potential of the read gate line GLb is set to 0. and select source and drain lines SL.

+i/2Vp is applied to each DL. Note that unselected gate lines GLa, GLb and sources.

The signals applied to the drain lines SL and DL are the same as in the above writing. When such a voltage signal is applied, an opposite potential difference corresponding to the write/erase voltage VP is generated between the write/erase gate electrode Ga and the source/drain electrodes S, D of the memory transistor TIO of the selected memory element M. At this time, a voltage of 1 is applied between the gate electrode Ga and the source and drain electrodes S and D of the selection transistors T20a and T20b on both sides of the memory transistor TIO, similarly to the memory transistor T10. Normally, in a thin film transistor whose semiconductor layer is made of amorphous silicon, polysilicon, or the like, even when a high negative voltage is applied to the gate electrode, conduction occurs between the source and drain, and the thin film transistor is turned on. Therefore, selection transistor T2
0a and T20b are turned on by a high negative voltage -P, and the data held in the memory transistor TIO is erased. Also in this case, the write/erase gate electrode Ga and source of the memory transistor TIO of the unselected memory element M.

The potential difference generated between drain electrodes S and D is 1/2VP
This memory transistor TIO is in an erasure inhibited state.

On the other hand, during reading, as shown in FIG. 1(c), among the selected gate lines GLa and GLb, VON is applied to the read gate line GLb, and V Sl:L is applied to the write/erase gate line GLa. At the same time, select source and drain lines SL.

VD is applied to the drain line DL of DL, and the potential of the source line SL is set to 0. In addition, the above VON and VD
is the write/erase voltage Vp of the memory transistor TIO
(40V), for example, V O
N-tov 5vD-10V. Also V Sl! L
is, for example, OV. Further, Vopp (for example, OV) is applied to the unselected read gate line GLb and write/erase gate line GLa, and the potentials of the unselected source and drain lines SL and DL are set to O.

When such a voltage signal is applied, the memory transistors T20a and T20b of the selected memory element M will receive the V applied to the read gate line GLb. Since it is turned on by N, a current flows from the drain line DL to the source line SL in accordance with the data held in the memory transistor TIO, and this is output as read data. In this case, a memory transistor TIO and a pair of selection transistors T20a.

Since it is connected in series with T20b, the voltage Vc applied to the read gate electrode G'b of the selected memory element M
b Characteristics of drain current ID (V,
b-ID characteristics) are for each transistor TIO.

Although the characteristics of T20a and T20b overlap, the read data is from each transistor TIO and T20a.

It is determined depending on the total characteristics of T20b. FIG. 3 shows the applied voltage VGa (VsgL) of the write/erase gate electrode Ga.
) is Ov of the selected memory element M. b-10
The characteristics of the memory transistor TIO are shown in (a).
VGb-ID characteristics, (b) is the selection transistor T20
a, v, b-ID characteristics of T20b, (C) each transistor Tl01T20a.

The total V and b-ID characteristics of T20b are shown.

In the figure, W is the characteristic in the write state, E is the characteristic in the erase state, and the drain current 1p when reading is selected.
is IDE when the memory transistor TIO is in the erased state, and is IDW(OA) when the memory transistor TIO is in the written state. That is, this memory element M is turned on in the erased state when reading is selected, and is turned off in the written state. Note that when reading is not selected, the write/erase gate line GLa and the read gate line GLb are
V (,pp) applied to the selection transistor 72
0a and T20b are in the OFF state, so the erase state is
Regardless of the write state, the memory module M is in the off state.

In addition, FIG. 3 shows the selected memory element when the voltage Vc a (VSEL) applied to the write/erase gate electrode Ga is set to +5V to +IOV (a voltage that does not cause a change in the erased state or written state of the memory transistor TIO). V of M. b-In characteristics, (a) is the memory transistor TIG(') Vab-1o characteristic, (b) is the Vab-In characteristic of the selection transistors T20a and T20b, and (c) is each transistor TIO, T20a, T2.
0b shows the total V c b -1p characteristic. When a certain voltage (+5V to +10V) is applied to the write/erase gate electrode Ga in this way, the memory transistor TlO and the selection transistors 720a, T2
Since the Vcb ID characteristic of 0b shifts to one side and the total VGb-ID characteristic shifts to one side, the drain current IDE when the memory transistor TIO is in the erased state can be increased.

At this time, the voltage applied to the readout gate line GLb during readout selection and non-selection may also be shifted to one side by the amount that the characteristics are shifted to one side.

In addition, in any of the above write, erase, and read operations, the voltage applied to the selected source and drain lines SL and DL is also applied to the unselected memory elements M on the source and drain lines SL and DL. However, the selection transistors 720a and T20b of this unselected memory element M
whose gate potential is negative voltage -1/2Vp or voF
Since the memory transistor TIO of the unselected memory element M is in an off state due to F(Ov)teal, it is not affected by the applied voltage. That is, also in this thin film transistor memory, the selection transistor T20a.

T20b not only selects the memory transistor TIG but also functions as a guard transistor that guards the memory transistor TIO from the voltage applied when it is not selected.

Next, a specific structure of the thin film transistor memory will be explained.

4 and 5 are a cross-sectional view and a plan view of one memory element M of a thin film transistor memory. To explain the structure of this memory element M, reference numeral 11 in the figure is an insulating substrate made of glass or the like, and on this substrate 11 are thin film transistors TIO, T20a, T20 for memory and selection.
A write/erase gate electrode Ga shared by the write/erase gate electrode Ga and a write/erase gate line GLa connected to the write/erase gate electrode Ga are formed. In addition, the substrate 11
Above, both sides of the write/erase gate electrode Ga except for the central part (each selection transistor 720a) are shown.

Thick film gate insulation [1
12 and a thin gate insulating film 13 that covers the entire write/erase gate electrode Ga. Each of the gate insulating films 12 and 13 is formed of silicon nitride (SIN) in which the composition ratio Si/N of silicon atoms S1 and nitrogen atoms N is almost the same as the stoichiometric ratio (Si/N-0.75). The thickness of the thick gate insulating film 12 is approximately 2,500 Å to 3,500 Å.
The thickness of the thin gate insulating film 13 is approximately 500 Å to 1500 Å. In other words, this lower gate insulating film is
The selection transistors T20a and T20b on both sides of the write/erase gate electrode Ga are a two-layer film in which the thin gate insulating film 13 is laminated on the thick gate insulating film 12, and the memory transistor 2710 in the center is a thin film. It is a single layer film consisting only of the gate insulating film 13. The lower gate insulating film 13 of this memory transistor 2710 portion
Because of its thin film thickness, it has a charge storage function even if its composition ratio S1/N is almost the same as the stoichiometric ratio.

Note that the lower gate insulating films 12 and 13 of the selection transistors 720a and T20b do not have a charge storage function because their entire film thickness is thick. Further, on the lower gate insulating film (on the thin gate insulating film 13), a memory transistor TIO and selection transistors T20a and T20a are arranged so as to face the entire area of the write/erase gate electrode Ga.
2Qb (type semiconductor layer 14 is formed. This i-type semiconductor layer 14 is made of 1-a-Sl (i-type amorphous silicon).
On both sides above the type semiconductor layer 14, n”-a-Sl (n
A source electrode S and a drain electrode are formed via an n-type semiconductor layer 15 made of amorphous silicon doped with type impurities, and the source electrode SIO is connected to a source line SL integrated therewith, and the drain The electrode is connected to a drain line DL which is integrated therewith. Reference numeral 16 denotes an upper gate insulating film (a film having a composition ratio Sl/N approximately equal to the stoichiometric ratio) having no charge storage function and formed on the i-type semiconductor layer 14 and the source and drain electrodes S and D. On top of this upper gate insulating film 16 are thin film transistors T10°T20a, T20a, and T20a for memory and selection.
A read gate electrode Gb shared by T20b and a read gate line GLb connected to this read gate electrode Gb are formed.

This read gate line GLb is formed directly above the write/erase gate line GLa, and is also connected to the write/erase gate line GLa and the read gate line G.
Lb is wired along an extension line of the write/erase gate electrode Ga and the read gate electrode Gb.

Note that in this embodiment, the write/erase gate line GL
a and the read gate line GLb are formed to have the same width as the write/erase and read gate electrodes Ga and Gb.

That is, in the thin film transistor memory of this embodiment, the memory element M has a structure in which a memory transistor TIO and two selection transistors 720a and T20b forming a pair therewith are formed in one thin film transistor. The TIO includes a write/erase gate electrode Ga, a lower gate insulating film having a charge storage function consisting only of a thin gate insulating film 13, and an i-type semiconductor layer 1.
4 and n-type semiconductor layer 15, source and drain electrodes S
, D, and an upper gate insulating film 16 without a charge storage function.
and a reading gate electrode Gb, and each of the selection transistors T20a and T20b is composed of the write/erase gate electrode Ga and a gate insulating film 12, 13 of two layers, a thick film and a thin film, without a charge storage function. a lower gate insulating film, the i-type semiconductor layer 14 and the n-type semiconductor layer 15
, the source and drain electrodes S and D, the upper gate insulating film 16, and the reading gate electrode Gb.

FIG. 6 shows a method of manufacturing the above-mentioned thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, a metal film such as chromium is deposited on the substrate 11, and this metal film is patterned to form a write/erase gate electrode Ga and a write/erase gate electrode connected to this gate electrode Ga. An erase gate line GLa is formed at the same time, and a thick gate insulating film 12, which is a lower gate insulating film, is deposited over the entire surface of the substrate 11.

Next, as shown in FIG. 6(b), a substantially central portion of the gate electrode Ga in the thick gate insulating film 12 is removed by etching to expose the write/erase gate electrode Ga in the memory transistor 2710 portion. let

Thereafter, as shown in FIG. 6(C), a thin gate insulating film 13, which is a lower gate insulating film, is deposited over the entire surface of the substrate 11, and on top of that, an i A type semiconductor layer 14, an n type semiconductor layer 15 made of n''-a-81, and one metal film such as chromium, which will become the source and drain electrodes S and D, are deposited in sequence.

Next, as shown in FIG. 6(d), the metal film 19 and n
The i-type semiconductor layer 15 is patterned to form a source electrode S and a source line SL, and a drain electrode and a drain line DL, and then the i-type semiconductor layer 14 is patterned into the shape of a memory element region.

After this, an upper gate insulating film 16 and a metal film such as chromium are sequentially deposited over the entire surface of the substrate 11, and this metal film is patterned into the shape of the read gate electrode Gb and the read gate line GLb. The thin film transistor memory shown in FIGS. 4 and 5 is completed.

FIG. 7 shows the circuit of the above-mentioned memory element M, and FIG. 8 shows its equivalent circuit, and each memory element M shown in FIG.
The circuit corresponds to the equivalent circuit in FIG.

In this thin film transistor memory, since each memory element M has a configuration in which selection transistors 720a and T20b are provided in series on both sides of the memory transistor TIO, the pair of selection transistors T
Even if the characteristics of either T20a or T20b are defective, the memory transistor TIO can be selected and guarded by the other selection transistor.
Therefore, reliability can be improved. Moreover,
In this thin film transistor memory, by providing a reading gate electrode Gb in the memory transistor TlO and the selection transistors 720a and T20b, writing and erasing can be performed using the original gate electrodes (gate electrodes for write erasure) of the selection transistors T20a and T20b and the memory transistor TIO. ) by applying a gate voltage to Ga,
For reading, select transistor 720a is used.

A gate voltage is applied to T20b and the reading gate electrode Gb of the memory transistor TIO, and in this way reading is performed between the selection transistors 720a, T
20b and the reading gate electrode Gb of the memory transistor TIO, it is necessary to apply a gate voltage that changes the threshold voltage of the memory transistor TIO to the original gate electrode Ga of the memory transistor Tlo during reading. Therefore, it is possible to perform semi-permanently stable reading by eliminating changes in the threshold voltage of the memory transistor Ta due to repeated reading.

Further, in the thin film transistor memory of the above embodiment, the memory transistor TIO, the selection transistor 720a,
The write/erase gate electrode Ga of T20b is connected as an integrated electrode to a common write/erase gate line GLa, and the memory transistor TIO and the read gate electrode Gb of the selection transistors T20a, T20b are integrated. This read gate electrode Gb is connected to a common read gate line GLb as an electrode for applying a signal to the write/erase gate electrode Ga or the read gate electrode Gb of the memory transistor TIO and the selection transistors 720a and T20b. Since the writing is performed from the common write/erase gate line GLa or read gate line GLb, the memory transistor TIO and selection transistors T20a, T2
0b and a readout gate electrode Gb, the number of gate lines is the same as that of the conventional thin film transistor memory. Moreover, in the above embodiment, the write/erase gate line GLa and the read gate line GLb are wired along the extension line of the write/erase gate electrode Ga and the read gate electrode Gb, so they are lined up in the gate line direction. There is no need to take up wiring space for gate lines on the sides of the memory element array, and therefore the degree of integration can be increased accordingly.

Further, in the thin film transistor memory of the above embodiment, the memory element M is formed by combining the memory transistor TIO and the selection transistors T20a and T20a in one thin film transistor.
20b, the element area of each memory element M can be made very small, and the degree of integration can be further increased.

Note that in this embodiment, the write/erase gate line GL
a and the readout gate line GLb are connected to the gate electrode Ga,
This gate line GL is formed at the same convergence as Gb.
The widths of a and GLb may be smaller than the gate electrodes Ga and Gb, and in that case, the write/erase gate line GLa
The reading gate line GLb and the reading gate line GLb may be wired with their positions shifted from each other.

Next, another embodiment of the present invention will be described.

9 and 10 show a second embodiment of the present invention, and FIG. 9 shows a cross section of one memory element M of a thin film transistor memory. Components in the drawings that correspond to the first embodiment shown in FIGS. 4 and 5 are designated by the same reference numerals and their explanations will be omitted.

As shown in FIG. 9, the thin film transistor memory of this embodiment has a memory transistor TIO of the memory element M.
The lower gate insulating film is a non-memory film made of silicon nitride (SiN), which has no charge storage function and has a composition ratio S i /N almost the same as the stoichiometric ratio (Sl / N - 0.75). An insulating film 17 and a memory insulating film 18 made of silicon nitride with a composition ratio St/N larger than the stoichiometric ratio (St/N-0.85 to 1.15) to have a charge storage function. The selection transistor "IJOa" is made of a layered film.

The lower gate insulating film of T20b is made up of only the non-memory insulating film 17, and the non-memory insulating film 17 is
Thin film transistors TIO and T20 for memory and selection
a, Gate electrode G for writing and erasing shared by T20b
It is formed on top of a, covering the entire area. Further, the memory insulating film 18 is formed on the non-memory insulating film 17.
It is formed to face the portion of the write/erase gate electrode Ga that becomes the gate electrode of the memory transistor TIO (the central portion of the write/erase gate electrode Ga). In addition,
The thickness of the non-memory insulating film 17 is approximately 2000 Å, and the memory insulating film 18 is an extremely thin film with a thickness of 100 nm.

The thin film transistor memory of this second embodiment also includes a memory transistor TIO and two selection transistors T20a in one thin film transistor.
The memory transistor TIO has a structure in which a write gate electrode Ga, a lower gate insulating film consisting of a non-memory insulating film 17 and a memory insulating film 18, and an i-type semiconductor The selection transistors T20a and T20b are composed of a layer 14 and an n-type semiconductor layer 15, sos and drain electrodes S and D, an upper gate insulating film 16, and a readout gate electrode Gb, and each of the selection transistors T20a and T20b is
The write/erase gate electrode Ga, the lower gate insulating film made of the non-memory insulating film 17, the i-type semiconductor layer 14 and the n-type semiconductor layer 15, the source and drain electrodes S and D, and the upper It is composed of a gate insulating film 16 and the read gate electrode Gb. In this embodiment, the write/erase gate line GLa and the read gate line GLb are narrow lines, and the gate lines GLa and GLb are vertically opposed to each other to form memory element rows arranged in the gate line direction. Wired to the - side.

FIG. 10 shows a method of manufacturing the above-mentioned thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, a metal film such as chromium is deposited on the substrate 11, and this metal film is patterned to form a write/erase gate electrode Ga and this gate electrode Ga, as shown in FIG. 10(a).
A write/erase gate line GLa connected to the gate line GLa is simultaneously formed, and a non-memory insulating film 17 serving as a lower gate insulating film and a memory insulating film 18 are formed on the write/erase gate line GLa over the entire surface of the substrate 11.
and are sequentially deposited.

Next, as shown in FIG. 10(b), a portion of the memory insulating film 18 other than the memory transistor T10 portion is removed by etching, and then, as shown in FIG. 10(c), the entire surface of the substrate 11 is etched. , 1-a-5l, an n-type semiconductor layer 15 of n''-a-3l, and a metal film 19 made of chromium or the like that will become the source and drain electrodes S and D are successively deposited.

Next, as shown in FIG. 10 (CI), one metal film and the n-type semiconductor layer 15 are patterned to form a source electrode S.
A source line, a drain electrode, and a drain line are formed, and then the i-type semiconductor layer 14 is patterned in the shape of the memory element region.

After this, an upper gate insulating film 16 and a metal film such as chromium are sequentially deposited over the entire surface of the substrate 11, and this metal film is patterned into the shape of the read gate electrode Gb and the read gate line GLb. , the thin film transistor memory shown in FIG. 9 is completed.

The circuit of the memory element M of this second embodiment is the same as that shown in FIG. 7, and its equivalent circuit is shown in FIG.

Therefore, in the thin film transistor memory of the second embodiment, each memory element M has a structure in which the selection thin film transistors 720a and T20b are provided in series on both sides of the memory thin film transistor TIO. Even if the characteristics of either one of 720a and T20b are poor, the memory transistor TIO can be selected and guarded by the other selection transistor, thus improving the reliability of the memory transistor TIO. TIO
A reading gate electrode Gb is provided for each of the selection transistors T20a and T20b and the selection transistors T20b and the memory transistor T for reading.
Since the gate voltage is applied to the reading gate electrode Gb of the IO, there is no change in the threshold voltage of the memory transistor Ta due to repeated reading, and stable reading can be performed semi-permanently.

Also in this second embodiment, the memory transistor TIO and the selection transistor T20a.

The write/erase gate electrode Ga and the read gate electrode Gb of T20b are connected to a common write/erase gate line GL.
Since the number of gate lines is the same as that of conventional thin film transistor memory, the number of gate lines is the same as that of conventional thin film transistor memory. Since the space required for wiring is half that of conventional thin film transistor memory, it is possible to increase the degree of integration compared to conventional thin film transistor memory. Furthermore, in this second embodiment as well, the memory element M has a structure in which the memory transistor TIO and the two selection transistors 720a and T20b are formed in one thin film transistor, so that the element area of the memory element M can be reduced. In this way, the degree of integration can be further increased.

In the first and second embodiments described above, each memory element M of the thin film transistor memory has a structure in which a memory transistor TIO and two selection transistors T20a and T20b are formed in one thin film transistor. Memory transistor 9 forming element M
．． 710 and two selection transistors T20a, T20
b may be separate thin film transistors, and in that case, the write/erase gate electrodes and read gate electrodes of the memory transistor and selection transistor are connected to a common write/erase gate line and read gate as in the above embodiment. If connected to a line, the number of gate lines is the same as that of conventional thin film transistor memory. However, when the memory transistor and the two selection transistors are separate thin film transistors in this way, the write/erase gate electrode and the read gate electrode of the memory transistor and the selection transistor may be connected to separate gate lines. In that case, the gate line, source, and drain lines for programming and erasing should be
), (b) are applied for writing and erasing, and the signals shown in FIG. 1(C) are applied to the read gate line, source, and drain lines for reading. Good too.

〔Effect of the invention〕

In the thin film transistor memory of the present invention, selection thin film transistors are provided in series on both sides of the memory thin film transistor, and each of the memory thin film transistor and the selection thin film transistor is located on the side opposite to its gate electrode and has a charge storage function. Since the readout gate electrode is provided facing the semiconductor layer through a gate insulating film, even if one selection thin film transistor has poor characteristics, the other selection thin film transistor can select the other selection thin film memory transistor. The reliability can be greatly improved, and if reading is performed by applying a gate voltage to the read gate electrodes of the selection thin film transistor and the memory thin film transistor, the memory Since there is no need to apply a gate voltage that would change the threshold voltage of this transistor to the original gate electrode of the thin film transistor for memory, it is possible to eliminate changes in the threshold voltage of the thin film transistor for memory due to repeated reading and to achieve semi-permanently stable reading. can be done.

[Brief explanation of drawings]

1 to 8 show a first embodiment of the present invention. FIG. 1 is a circuit diagram of a thin film transistor memory, and FIGS. 2 and 3 are a circuit diagram of a thin film transistor memory, respectively. Drain current characteristics versus applied voltage; Figures 4 and 5 are cross-sectional views and plan views of one memory element of a thin film transistor memory; Figure 6 is a manufacturing process diagram of the thin film transistor memory; Figures 7 and 8 are diagrams of the memory. 2 is a circuit diagram of an element and its equivalent circuit diagram. FIG. Figures 9 and 10
The figures are a sectional view of one memory element of a thin film transistor memory and a manufacturing process diagram thereof showing a second embodiment of the present invention. FIG. 11 is a circuit diagram of a conventional thin film transistor memory. M...Memory element, TlO...Thin film transistor for memory, T20a, T20b...Thin film transistor for selection, Ga...Gate electrode for writing and erasing, 12.1
3... Lower gate insulating film (12... Thick film gate insulating film, 13... Thin film gate insulating film, 17.18... Lower gate insulating film (17... Non-memory insulating film, 18・
... memory insulating film), 14... i-type semiconductor layer, 15
... n-type semiconductor layer, 16 ... upper gate insulating film, G
b...Reading gate electrode, S...source electrode, D
...Drain electrode, GLa...Gate line for writing and erasing, GLb...Gate line for reading, SL...
・Source line, DL...Drain line. Figure 1 Figure 7 Figure 8 Figure 3 (c) Figure 4 Figure 5

Claims (1)

[Claims] In a thin film transistor memory comprising a memory thin film transistor and a selection thin film transistor for selecting the memory thin film transistor, the selection thin film transistor is provided in series on both sides of the memory thin film transistor, and the memory thin film transistor and the selection thin film transistor are provided with: A thin film transistor memory characterized in that a second gate electrode for reading is provided opposite to the gate electrode and facing the semiconductor layer via a gate insulating film having no charge storage function.