JPH0360583A - Television receiver - Google Patents

Abstract

PURPOSE:To attain excellent image reception by a receiver for High Vision or the like by varying a phase of a vertical synchronizing signal to shift a displayed video image in the vertical direction and converting the vertical synchronizing signal into a pseudo vertical synchronizing signal for image reception. CONSTITUTION:A vertical synchronizing processing circuit 10 changes a phase by a quantity based on an adjustment data obtained from an external device and supplies an outputted pseudo vertical synchronizing signal VD to a deflection circuit 9. Then based on a horizontal synchronizing signal 2HD and the pseudo vertical synchronizing signal VD supplied to the deflection circuit 9, the horizontal and vertical deflection of an electron beam of a cathode ray tube 8 is controlled and the video image based on the signal fed from a video processing circuit 7 to the cathode ray tube 8 is displayed on the cathode ray tube 8. When a video signal of the NTSC system is displayed on a High Vision cathode ray tube 8, the displayed position is shifted vertically only by setting the adjustment data.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Conventional technology D. Problem to be solved by the invention E. Means for solving the problem (Figure 1, Diagram 1) F
Effect G Embodiment G1 Overall configuration G2 Configuration of vertical synchronization processing circuit G3 Operation during image reception G4 Operation of vertical synchronization processing circuit The present invention relates to a television receiver that is suitable for application to a television receiver.

B. Summary of the Invention The present invention is applicable to high-definition video signals and NTSC.
In a television receiver that can selectively receive video signals of two types of aspect ratios, such as a video signal of the same format, the phase of the vertical synchronization signal of the video signal is digitally changed,
This makes it possible to easily adjust the display position of the video while blanking the signals of the portions that are not to be displayed.

C. Prior Art In recent years, video signal transmission systems that display high-resolution images called high-definition have been developed. In this high-definition system, the resolution of the image is not only increased, but also the width of the screen in the horizontal direction is widened, so that the screen is longer than the screen using normal video signals. The ratio between the horizontal width and the vertical width of the screen is called the aspect ratio, and while the screen aspect ratio with conventional normal video signals is 4:3, in high-definition systems, the aspect ratio is 16:9, for example. It is proposed to do so.

Therefore, when considering a television receiver that can receive both high-definition video signals and normal video signals such as the NTSC system, if the screen size is set for high-definition, the aspect ratio will change when receiving normal video signals. Part of the image is cut by the difference in ratio.

An example of how to receive an NTSC video signal on a high-definition aspect ratio screen is as follows: For example, in FIG. Suppose you want to display it on a screen with an aspect ratio. In this case, the screen size for high-definition is wider than the NTSC system, as shown in Figure 5, so if the image is to be displayed on the entire high-definition screen, the top or bottom of the original image will be cut off. .

That is, it is necessary to display the image by cutting off the lower part of the image, as shown in FIG. 5A, or by cutting off the upper part of the image, as shown in FIG. 5C. Alternatively, as shown in FIG. 5B, the upper and lower parts may be cut equally to display the central part.

Although various display states are possible as described above, it is desirable that the viewer be able to appropriately select the part to be cut depending on the position where what he or she wants to see is displayed.

D. Problem to be Solved by the Invention However, the circuit configuration that allows the display state to be changed in this way has the disadvantage of being complicated.

In other words, for example, if a DC bias current is superimposed on the vertical deflection current supplied to a cathode ray tube, the displayed image can be moved up and down by changing the amount of bias current. When bias current is superimposed, adjustment values such as bin distortion and convergence change,
Inconveniences such as image distortion occur, and complex circuitry is required to correct it. Also, if you use a frame memory to shift each horizontal scanning line, you can change the display state without adjusting the deflection system, but the frame memory and its peripheral circuits have a very large circuit configuration. There are disadvantages in that the configuration is complicated and the frame memory is expensive.

In order to solve this problem, the applicant first shifted the phase of the vertical synchronization signal by counting down with a counter.
He proposed a television receiver in which the display position could be changed (Japanese Patent Application No. 1-142373).

However, when constructing an actual high-definition television receiver, the vertical synchronization signal supplied to the receiver circuit must be a high-definition vertical synchronization signal, and the NTS
If you simply shift the vertical synchronization signal for C system,
It could not be displayed on a high-definition television receiver, and the canted portions of the image that were not to be displayed also required processing.

In view of this, an object of the present invention is to enable adjustment of the display position with a simple configuration while taking into account differences in signal states such as vertical synchronization signals when displaying images with different aspect ratios. do.

E. Means for Solving the Problems The television receiver of the present invention, for example as shown in the first factor, has a video signal having a first aspect ratio and a video signal having a second aspect ratio different from the first aspect ratio. signal and
In a television receiver that can selectively display images on the video display section (8) of a screen with a first aspect ratio, the vertical synchronization signal of the video signal with the second aspect ratio is converted into a horizontal synchronization signal for one screen. A conversion circuit (12) that converts into a pseudo vertical synchronization signal using a counter that counts based on the number of pulses.
, (13).

(15), (16), an adjustment means (14) for controlling the phase of this pseudo vertical synchronization signal to determine the overscan portion of the screen, and a pseudo vertical synchronization signal controlled by this adjustment means (14). and generating means (7e) for generating a vertical blanking period using the vertical blanking period.

F Function According to this configuration, the displayed image is shifted in the vertical direction by changing the phase of the vertical synchronization signal, and the display position is adjusted. In this case, the vertical synchronization signal is converted to a pseudo vertical synchronization signal for image reception, and the image is well received on a high-definition receiver, etc., and the overscan area is blanked, so the overscan area is Good image reception is achieved without adversely affecting the image.

G. Embodiment Hereinafter, an embodiment of the television receiver of the present invention will be described with reference to the accompanying drawings.

G1 Overall configuration In this example, the aspect ratio for high-definition (16
:9) television receiver equipped with a CRT, NTS
It is designed to be able to receive C-format video signals (aspect ratio 4:3) and high-definition video signals. That is,
In Fig. 1, (1) indicates a received signal input terminal to which a signal received from an antenna etc. is supplied, and this input terminal (
The received signal obtained in step 1) is supplied to a tuner (2), and the tuner (2) extracts a video signal of a desired channel. Further, (3) and (4) in the figure indicate a video tape playback device and a video disc playback device, and playback video signals are output from the playback devices (3) and (4), respectively.

Then, the video signal output from the tuner (2) is supplied to the first fixed contact (5a) of the changeover switch (5), and the video signal output from the videotape playback device (3) is supplied to the first fixed contact (5a) of the changeover switch (5). The second fixed contact (5b) is supplied to the second fixed contact (5b), and the video signal output from the video disc playback device (4) is supplied to the third fixed contact (5c) of the changeover switch (5). Then, the video signal obtained at the movable contact (5m) of this changeover switch (5) is supplied to the synchronization separation circuit (6). This synchronization separation circuit (6) separates the horizontal synchronization signal H and vertical synchronization signal ■ from the video signal, and the video signal and the horizontal and vertical synchronization signals H and ■ output from this synchronization separation circuit (6) are subjected to video signal processing. Supplied to circuit (7). The synchronization separation circuit (6) and the video signal processing circuit (7) are processing circuits for NTSC video signals in which the number of horizontal scanning lines in the L field period is 262.5, and the video signals for high-definition are M.U.
The signal is supplied to another circuit system (not shown) equipped with an SE signal decoder, etc., and is received by a cathode ray tube (8), which will be described later. however,
The deflection circuit (9) of the cathode ray tube (8) is shared by any video signal.

Then, in the video signal processing circuit (7), the video signal that performs so-called double-speed scanning (the number of horizontal scanning lines in one field period is 525), which doubles the number of horizontal scanning lines in one frame of the supplied video signal.
This converted video signal is subjected to signal processing for image reception and then supplied to a cathode ray tube (8). In this case, the display on the cathode ray tube (8) differs in aspect ratio between the NTSC system and the high-definition system, so as shown in Figure 5, when displaying an NTSC system video signal, one field has 64 pixels.
Cuts the horizontal scanning lines (number of scanning lines before double speed conversion) and enlarges and displays the remaining video. In addition, the video signal processing circuit (7) converts the horizontal synchronizing signal H into a horizontal synchronizing signal 2 for double-speed scanning.
Convert to HD (frequency signal twice the horizontal synchronization signal H),
This horizontal synchronizing signal 2HD is supplied to the deflection circuit (9).

In this example, the vertical synchronizing signal ■ outputted by the synchronizing signal separation circuit (6) and the horizontal synchronizing signal 21 (D) for double-speed scanning outputted by the video signal processing circuit (7) are connected to the vertical synchronizing signal 10).This vertical synchronization processing circuit (
10) is a circuit that changes the phase of the vertical synchronization signal (■) within a predetermined range and outputs a pseudo vertical synchronization signal VD converted into a high-definition vertical synchronization signal.The circuit changes the phase by an amount based on adjustment data obtained from the outside. The pseudo vertical synchronization signal VD output from the vertical synchronization processing circuit (10) is supplied to the deflection circuit (9).

Then, the horizontal synchronization signal 2HD obtained in the deflection circuit (9)
and a cathode ray tube (8) based on the pseudo vertical synchronization signal VD.
The horizontal and vertical deflections of the electron beam are controlled to cause the cathode ray tube (9) to display an image based on the signal supplied from the video signal processing circuit (7) to the cathode ray tube (9).

G2 Configuration of Vertical Synchronization Processing Circuit Here, the vertical synchronization processing circuit (lO) and its peripheral circuit configuration are shown in FIG. 2. First, the horizontal synchronization signal H for the NTSC system is The configuration for creating the horizontal synchronization signal 2HD for high-visibbon is shown below.
The horizontal synchronizing signal H obtained at the terminal (7a) of the video signal processing circuit (7) is supplied to a PLL (phase long loop) circuit (7b), and is multiplied by this PLL circuit (7b) to produce a clock signal CLK. to create. Then, the clock signal CLK is supplied to a frequency divider (7c) to obtain a horizontal synchronization signal 2HD as a frequency-divided signal. In this case, the horizontal synchronizing signal 2HD obtained by frequency division is supplied to the 172 frequency divider (7d), and the signal obtained by dividing the frequency by 1/2 by the 172 frequency divider (7d) is supplied to the PLL circuit (7b ) as a reference signal. By doing so, the video signal processing circuit (7) generates a stable horizontal synchronization signal 2HD and supplies it to the vertical synchronization processing circuit (10) and each circuit in the video signal processing circuit (7).

In the vertical synchronization processing circuit (10), the jitter removal circuit (1
1) Supply the vertical synchronization signal V. This jitter removal circuit (11) converts an NTSC vertical synchronizing signal V having a width of a predetermined horizontal scanning period into one horizontal scanning period for double-speed scanning.
It is converted into a pulse signal V' having a width of IH). The converted pulse signal V' is then supplied to the first counter (12) as a trigger pulse signal. Further, the horizontal synchronization signal 2HD outputted from the video signal processing circuit (7) is supplied to the first counter (12) as a clock signal. Then, the first counter (12) counts the horizontal synchronizing signal 2HD from the timing to which the IH width pulse signal v' is supplied, and when it counts 461 cycles (461H), the IH width pulse signal V" is counted. Output.Then, this pulse signal ■
" is supplied to the second counter (13) as a trigger pulse signal. Also, the horizontal synchronization signal 2HD output from the video signal processing circuit (7) is supplied to the second counter (13) as a clock signal. Then, the second counter (1
3) counts the horizontal synchronizing signal 2 HD from the timing to which the IH width pulse signal V'' is supplied, and outputs a count signal whose count value changes in the range of 0 to 127;
This count signal is supplied to one comparison signal input terminal of the comparator (14).

Further, (10b) in the figure shows an adjustment data input terminal, and adjustment data for controlling the display state is supplied to this input terminal (10b) from a central control unit (not shown) of each circuit of this television receiver. be done. In this case, as the adjustment data, a signal based on a count signal with a preset count value in the range of count values 0 to 127 is supplied, and this adjustment data is input to the other comparison signal input terminal of the comparator (14). supply When this comparator (14) detects coincidence between the count value indicated by the count signal supplied to one input terminal and the count value supplied as adjustment data, it outputs a coincidence pulse P.

This coincidence pulse P is then supplied to the third counter (15) as a trigger signal. The third counter (15) receives a horizontal synchronization signal 2H output from the video signal processing circuit (7).
D is supplied as a clock signal, and when this coincidence pulse P is supplied, counting of the horizontal synchronization signal 2HD is started, and the clock signal I is sent as, for example, 10-bit digital data to the pseudo vertical synchronization generation circuit (step 6). supply This pseudo vertical synchronization generation circuit (16) outputs a pseudo vertical synchronization signal VD which becomes a low level signal "I O1" when the count value indicated by the supplied count signal is 0 to 4 from the output terminal (10c) to the deflection circuit. (9). By generating the pseudo vertical synchronization signal VD in this way, 5
A vertical synchronization signal VD having a width of a horizontal scanning period (5H) and conforming to a high-definition vertical synchronization signal is obtained.

In addition, in this example, this pseudo vertical synchronization generation circuit (16
) detects that the count value indicated by the supplied count signal is, for example, 0 to 67 and 461 to 524, it sends a blanking control signal to the blanking circuit (7e) in the video signal processing circuit (7). Supply BLK. This blanking circuit (7e) blanks the video signal supplied from the synchronization separation circuit (6) to a constant level such as the black level while the blanking control signal BLK is supplied.

G3 Operation during image reception To explain the operation when receiving an image with the television receiver having the above configuration, first, the overall operation will be explained with reference to the time chart of FIG. 3.

The television receiver of this example can receive a video from a desired video signal source by switching the input video signal by switching the changeover switch (5). Here, N
When a video signal source from which a TSC system video signal can be obtained is selected, the video signal is supplied to the synchronization separation circuit (6),
From this video signal, the vertical synchronization signal V (
A) in FIG. 3 is extracted, and this vertical synchronization signal (2) is supplied to the video signal processing circuit (7) and the vertical synchronization processing circuit (10). Here, this vertical synchronization signal V is applied to the vertical synchronization processing circuit (
10), the second counter (13) in the vertical synchronization processing circuit (10)
) is supplied with a trigger pulse signal V'' (FIG. 3B),
When a predetermined period indicated by the adjustment data has elapsed since the trigger pulse signal was supplied, the third counter (15)
The pseudo vertical synchronization generation circuit (1
6) outputs a pseudo vertical synchronization signal VD. This pseudo vertical synchronization signal VD is output with a delay from the start signal by a period D+, Lz, and t, i) indicated by the adjustment data, as shown in FIGS. 3CD and E, for example. In this case, when the adjustment data is midpoint data (described later) (when the count value 64 is set by the adjustment data),
The pseudo vertical synchronizing signal VD output with a delay of the period t2 set at this time is the vertical synchronizing signal VD shown in FIG. 3A.
The phases become equal with a difference of one field period. Therefore,
By changing the adjustment data before this midpoint, a pseudo vertical synchronization signal VD whose phase is more advanced than the vertical synchronization signal V can be obtained, as shown in FIG. By changing, for example, as shown in FIG. 3, a pseudo vertical synchronization signal VD whose phase is delayed from that of the vertical synchronization signal V can be obtained.

Furthermore, by using a blanking control signal that blanks each of 64 horizontal scanning periods before and after the pseudo vertical synchronization signal VD, the video signal processing circuit (7
) A blanking interval is formed within the range. However, the example in FIG. 3F shows a case where the pseudo vertical synchronization signal has a phase as shown in FIG.

G4 Operation of Vertical Synchronization Processing Circuit Here, the operation of generating this pseudo vertical synchronization signal V' in the vertical synchronization processing circuit (10) will be explained with reference to the time chart of FIG. ), a trigger pulse signal V' having a pulse width of 1H as shown in FIG.
It is assumed that a horizontal synchronizing signal 2HD for double-speed scanning created in the above and shown in FIG. 4B is supplied to the vertical synchronizing processing circuit (10). At this time, the first counter (12) has
When it is detected that 461 cycles of the horizontal synchronizing signal 2HD have elapsed from the timing at which the vertical period trigger pulse signal v' rises, the trigger pulse signal v'' temporarily becomes a low level signal "°0" (Fig. 4). C) is output. When this trigger pulse signal " is supplied to the second counter (13), the 20th counter (13) starts counting the horizontal synchronization signal 2HD as shown in the fourth diagram. A count signal like this is output, and this count value is output to the terminal (10b).
When the count value coincides with the count value indicated by the adjustment data obtained in , a coincidence pulse P (FIG. 4E) which temporarily becomes a low level signal IfO11 is output. For example, the example in FIG. 4 shows a case where the count value 64, which is approximately the midpoint, is set by the adjustment data. And this coincidence pulse P is the third
When this counter (15) is supplied to the counter (15), this third counter (15) starts counting the horizontal synchronizing signal 2HD and outputs a count signal as shown in FIG. 4, the pseudo vertical synchronization generating circuit (16) outputs a pseudo vertical synchronization signal VD (FIG. 4G) which becomes a low level signal "°O".

Here, the count value indicated by the adjustment data is 0 to 1
The count at the middle point (IIF64 is the standard value.) When the adjustment data is set to the standard value, double-speed scanning is performed when receiving NTSC video signals, so the horizontal scanning line of one field The number is 525, but 461 horizontal scanning periods (while the first counter (12) counts 461) have elapsed from when the vertical synchronizing signal ■ is output until when the trigger pulse signal ■'' is output. When 64 horizontal scanning periods (while the second counter (13) counts 64) have elapsed since the trigger pulse signal V'' was output, the pseudo vertical synchronizing signal VD is output. The pseudo vertical synchronizing signal VD is output after (461+64) = 525 horizontal scanning periods have elapsed since the synchronizing signal V was output, and the pseudo vertical synchronizing signal VD is output with a delay of one field period. As shown in FIGS. 3A and 3D, there is no phase difference between the vertical synchronizing signal (2) and the pseudo vertical synchronizing signal VD.

Then, adjust the adjustment data to values around the standard value 64 (0 to 64).
127), vertical synchronization signal ■ and ±
A pseudo vertical synchronization signal VD with a 6464 horizontal scanning phase difference is output. The phase difference in this case is set for each horizontal scanning period.

By supplying the pseudo vertical synchronization signal VD created in this manner to the deflection circuit (9), the display position of the image displayed on the cathode ray tube (8) can be adjusted up and down.

That is, N is applied to the cathode ray tube (8) of the television receiver of this example.
When receiving a TSC video signal, as shown in Figure 5, several tens of horizontal scanning lines of the original video (indicated by dotted lines) are cut off, but the pseudo vertical synchronization signal VD is cut out by one horizontal scanning line depending on the adjustment data. Since it changes every scanning period, by changing the count value indicated by the adjustment data, the displayed image can be changed to 1.
You can move the horizontal scan line up or down. At this time, when the count value indicated by the adjustment data is close to the minimum value O, as shown in FIG. 1
When the value is close to 27, more horizontal scanning lines at the top of the screen are cut, as shown in FIG. 5C. Further, when the standard value is set to 64, as shown in FIG. 5B, the top and bottom of the screen are cut almost equally, and the center portion is displayed.

In this example, the pseudo vertical synchronization generation circuit (16)
to the blanking circuit (7) in the video signal processing circuit (7).
As shown in FIG. 4H, the blanking control signal BLK supplied to e) becomes low level at the cut portion before and after the pseudo vertical synchronization signal VD (i.e., the overscan portion), so the overscan portion is ensured. A blanking process is applied to the

In this way, according to the television receiver of this example, the NTS
When displaying C format video signals on a high-definition cathode ray tube (8), the display position can be moved up or down just by setting adjustment data, making it easy to adjust the display position without adjusting the deflection circuit, etc. I can do it. In this case, the pseudo vertical synchronization signal VD is generated as a high-definition vertical synchronization signal by the pseudo-vertical synchronization generation circuit (step 6), so that it can be well received by the high-definition cathode ray tube (8).

Further, in this example, a pseudo vertical synchronization signal VD
Since the blanking control signal BLK is created according to the phase of I won't give it.

Furthermore, in this example, the horizontal synchronization signal 2HD for double-speed scanning used as a clock signal in the vertical synchronization processing circuit (10) is created in the video signal processing circuit (7), so the video signal processing circuit The timing of processing the video signal in (7) is performed in a state in which the phase matches the pseudo vertical synchronization signal VD created by the vertical synchronization processing circuit (10).

In the above embodiment, a case has been described in which a high-definition receiver receives an NTS C video signal, but the present invention is not limited to this method, and can also be used to receive video signals with different aspect ratios. Of course, it can be applied to various cases of image reception.

H Effects of the Invention According to the television receiver of the invention, when the aspect ratio set by the video signal is different from the aspect ratio of the display screen, the display position can be easily adjusted. In this case, the blanking section changes in conjunction with the adjustment of the display position, and there is an advantage that the overscan section is always blanked and good image reception is performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the television receiver of the present invention, FIG. 2 is a block diagram of the main parts of the example in FIG. 1, and FIGS. 3 and 4 are explanations of the example in FIG. 1, respectively. FIG. 5 is a route map used to explain the display state. (7) is a video signal processing circuit, (7e) is a blanking circuit, (8) is a cathode ray tube, (10) is a vertical synchronization processing circuit,
(16) is a pseudo vertical synchronization generation circuit. - Figure 1: Configuration diagram of the lol example

Claims (1)

[Claims] A video signal having a first aspect ratio and a video signal having a second aspect ratio different from the first aspect ratio are selectively displayed on the video display portion of the screen having the first aspect ratio. In a television receiver capable of displaying images, the vertical synchronization signal of the video signal of the second aspect ratio is
A conversion circuit converts the horizontal synchronization signal into a pseudo vertical synchronization signal using a counter that counts based on the number of pulses of the horizontal synchronization signal for one screen, and controls the phase of the pseudo vertical synchronization signal to control the overscan part in the screen. What is claimed is: 1. A television receiver comprising: an adjusting means for determining a vertical blanking period; and a generating means for generating a vertical blanking period using a pseudo vertical synchronizing signal controlled by the adjusting means.